Abstract

Finite Impulse Response (FIR) filtering and LeastMean Squares (LMSI adaptive filtering algorithms have been implemented in both hardware and sofnvare on a MicroblaEe processor configured in a Virrer II, runnirig aClinxr. These implementarions have been ewluared in terms of currenr usage (both idle and active). area usage (for hardware-assisted implemenrarions), latency and CPU urilisarion. Partitioning of the MS algorithm was initially performed in U simple way, highlighring rhe shortcomings of obvious partitioning arrangements.A , 5111 implementation showed the advantages in terms of increased power eficiency (5.7m4 consumed, compared to 60.4mA for the sofnvare imnplementarionj. Hardware implementations were found to be generall? more power eflcienr, although increased idle power usage (11.3mA extra for the idle LMS imnplementarionj may negate the savings if the [ask is nut erecured regularly.

The performance of programmable logic controllers is often constrained by the microprocessor and the real-time firmware of the controller. Field programmable gate arrays (FPGAs) are an attractive potential implementation medium for high-speed control because of their fast and parallel execution and programmable nature. Ladder Diagrams are a standard graphical programming method for industrial controllers, but compilers from Ladder Diagrams to FPGA hardware do not yet exist. This paper explores the comparative speed of four different classes of FGPA implementation of Ladder Diagrams -Interpreted Software, Compiled Software, Interpreted Hardware and Compiled Hardware. It also explores parallel versus serial execution of Ladder Diagrams in hardware, and identifies timers as a major resource user in parallel implementations. Overall, a Shared Timer Serial Compiled Hardware system for FPGA implementation of Ladder Diagrams is recommended. Using comparable FPGA resources to other alternatives it provides a 20-600 times speed improvement over other solutions whilst maintaining correct Ladder Diagram semantics.

No abstract

This paper introduces a computer architecture suitable for embedded real-time applications where low power consumption is a requirement. This is achieved through the use of a hybrid hardware-software system. A system architecture is proposed which allows for modules of a system to be implemented at run-time in either hardware or software. Implementation choices may be made dynamically based on the loading of the host microprocessor, in a multi-tasking environment. An approach to inter-module communication is described, along with how this is affected by dynamic configuration. Some research goals are identified, including investigating the effects on real-time performance, power consumption and the design process involved in reconfigurable systems.