Evaluating software and hardware implementations of signal-processing tasks in an FPGA

Abstract

Finite Impulse Response (FIR) filtering and LeastMean Squares (LMSI adaptive filtering algorithms have been implemented in both hardware and sofnvare on a MicroblaEe processor configured in a Virrer II, runnirig aClinxr. These implementarions have been ewluared in terms of currenr usage (both idle and active). area usage (for hardware-assisted implemenrarions), latency and CPU urilisarion. Partitioning of the MS algorithm was initially performed in U simple way, highlighring rhe shortcomings of obvious partitioning arrangements.A , 5111 implementation showed the advantages in terms of increased power eficiency (5.7m4 consumed, compared to 60.4mA for the sofnvare imnplementarionj. Hardware implementations were found to be generall? more power eflcienr, although increased idle power usage (11.3mA extra for the idle LMS imnplementarionj may negate the savings if the [ask is nut erecured regularly.

On the Power Consumption of Security Algorithms Employed in Wireless Networks

“…In particular, for FPGAs, only the power consumption of certain matrix multiplication algorithms have been presented in [1] and of various digital signal processing modules in [2]. Moreover, Lysecky and Vahid [3] have studied the differences between the performance achieved when certain tasks are executed in the embedded processing cores of a state-of-the-art-FPGA and when their are executed by dedicated hardware modules.…”

FPGA Implementation of an Adaptive Noise Canceller

“…There are usually two ways to implement the LMS algorithm, hardware implementation and software implementation [8], [9]. The hardware implementation of the algorithm in an FPGA has good real-time ability, but requires large resources.…”

Hardware and software development for the efficient mapping of mathematical problems on field programmable gate array systems

“…Hardware power measurements of large FPGAs has received little attention compared to that of standard cell ASIC, which has been extensively studied in the literature. In particular, only the power consumption when certain matrix multiplication algorithms are implemented in hardware have been presented in [27] and of various digital signal processing modules in [28]. Moreover, Lysecky and Vahid [29] have studied the differences between the performance achieved when certain tasks are executed in the embedded processing cores of a state-of-the-art-FPGA and when their are executed by dedicated hardware modules.…”