Increasing transistor switching time and rising count of transistors integrated over a chip area has given a high pace in computing systems by several orders of magnitude. With the integration of circuits, number of gates and transistors are increasing per chip area. CMOS Logic family is preferred due to its performance and impeccable noise margins over other families. However with integration in every digital circuit, the energy due to switching of gate doesn't decrease at same rate as gates are increased per chip area. Due to this, power dissipation becomes significant and also reduction of heat becomes more complicated and expensive. In CMOS based circuits dynamic power requirement is becoming major concern in digital circuits. In this paper, the work is focused on reducing the power dissipation in circuits which is increasing with down scaling of circuits. The work is done on 2:1 multiplexer and full adder circuit. Adiabatic logic with positive feedback (PFAL) is applied to redesign the circuit with input power taken as sinusoidal source of 3.3 V and analysis is done for power dissipation between conventional CMOS and PFAL based CMOS circuits. In comparison with the conventional CMOS 2:1 multiplexer circuit, the designed PFAL CMOS 2:1 multiplexer circuit has less power dissipation as 80.871 picoWatts while conventional CMOS circuit has 6.9090 nanoWatts with the same behavior of circuit. Also for full adder conventional CMOS circuit have 48.0452 picoWatts while PFAL based full adder has 3.9089 picoWatts.

Increasing transistor switching time and rising count of transistors integrated over a chip area has given a high pace in computing systems by several orders of magnitude. With the integration of circuits, number of gates and transistors are increasing per chip area. CMOS Logic family is preferred due to its performance and impeccable noise margins over other families. However with integration in every digital circuit, the energy due to switching of gate doesn’t decrease at same rate as gates are increased per chip area. Due to this, power dissipation becomes significant and also reduction of heat becomes more complicated and expensive. In CMOS based circuits dynamic power requirement is becoming major concern in digital circuits. In this paper, the work is focused on reducing the power dissipation in circuits which is increasing with down scaling of circuits. The work is done on 2:1 multiplexer and full adder circuit. Adiabatic logic with positive feedback (PFAL) is applied to redesign the circuit with input power taken as sinusoidal source of 3.3 V and analysis is done for power dissipation between conventional CMOS and PFAL based CMOS circuits. In comparison with the conventional CMOS 2:1 multiplexer circuit, the designed PFAL CMOS 2:1 multiplexer circuit has less power dissipation as 80.871 picoWatts while conventional CMOS circuit has 6.9090 nanoWatts with the same behavior of circuit. Also for full adder conventional CMOS circuit have 48.0452 picoWatts while PFAL based full adder has 3.9089 picoWatts.

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The millimeter wave technology has made its way to the 5G technology as the system of 5G requires larger bandwidth, higher frequency and system capacity. In order to achieve these parameters, the millimeter wave antenna research becomes necessary. The current wireless technologies require huge bandwidth which makes the spectrum of millimeter wave a potential candidate. Microstrip antennas have always been in an increasing demand due to their exceptional performance in the applications of wireless communication. The advantages of microstrip patch antenna led to its popularity among the researchers.The technologies such as MIMO, CMOS and beam forming are used with millimeter wave antenna for improving the mobile phone performance. There are various designs of microstrip patch antenna related to 5G technology and applications in the millimeter wave band which are discussed in the paper.

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