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The synchronous reference frame phase-locked loop (SRF-PLL) is a widely used synchronization technique in power electronics and power systems applications due to its ease of implementation and robust performance. The conventional SRF-PLL is a type-2 control system due to the use of proportional-integral controller as loop filter. With higher bandwidth design, it can achieve fast detection of frequency and phase under ideal grid conditions. However, its bandwidth should be sufficiently lowered to obtain proper disturbance rejection under unbalanced and distorted grid conditions. This results in a slower detection speed. Recently, several advanced PLLs with pre/in-loop filtering stage have been proposed to improve the detection speed. A major challenge with the PLLs is how to further improve their dynamic performance without compromising the disturbance rejection capability and stability. To resolve this issue, in this paper, a novel type-1 frequencylocked loop (FLL) is proposed. The disturbance rejection capability of the proposed FLL is improved using a modified structure low-pass filter with selective harmonics filtering ability. As the proposed FLL is type-1 control system, it achieves better dynamic performance with higher stability margins. The effectiveness of the proposed FLL is confirmed through experimental results and comparison with advanced type-2 PLLs.

Fault ride-through (FRT) operation has been a challenge for the doubly fed induction generator (DFIG) based wind turbines (WTs) as the stator winding is directly connected to the grid. Additionally, several grid codes have been established for the grid interconnection of WTs, which demand the WT to stay connected and provide the predefined reactive current support to the grid during FRT operation. The series voltage compensation (SeVC) based FRT schemes for DFIG WTs outperforms all others in terms of smooth transient performance. However, such FRT schemes require an additional voltage-source converter (VSC) and a bulkier series transformer to provide the SeVC. This paper proposes a low component count SeVC scheme that is applicable to both individual WTs and wind parks to cope up with the recent grid codes requirements. The proposed configuration eliminates the need of a series transformer and an additional VSC for the SeVC operation with the use of three additional IGBTs/switches. Furthermore, a coordinated control strategy is proposed to control the WT that enhance its FRT capabilities. The proposed low component count FRT scheme and coordinated control strategy are validated using the detailed mathematical modeling and simulation of 1.5 MW DFIG WT.Index Terms-Doubly fed induction generator (DFIG), fault ride through (FRT), grid faults, nine-switch converter, series voltage compensation (SeVC), unbalance, wind turbine (WT). 0885-8969