Over the past four decades, single event upset (SEU) and single event multiple node upset (SEMNU) have become the major issues in the memory area.Moreover, these upsets are prone to reliability issues in space, terrestrial, military, and medical applications. This article concisely reviews different researchers and academicians who proposed resilience techniques and methods to mitigate this upset mess. In addition, we also investigated the importance of Q Crit and the impact of Q Crit on device scaling parameters in upset mechanism, probability of memory failure, and the figure of metrics for the stability of memory cells.critical charge, figure of metric, single event upset, single event multiple node upset, soft error
| INTRODUCTIONTo enhance the functionality of system-on-chip (SoC), designers scale down the dimensions of the transistors. 1 According to the international technology roadmap for semiconductors (ITRS) prediction on memory size, and its processing engines on mobile type SoC, it is expected to rise by a factor of 18 between 2013 and 2025, 2,3 which is shown in Figure 1. Massive increasing the transistor count certainly increases the power consumption and degrade the mobile battery's life.Recent SoCs are embedded with static random access memory (SRAM) memories due to the faster and more reliable read/write approaches. Therefore, these SRAMs are used as cache and main memories. Moreover, SRAM memories occupy a maximum area on SoC's. 2 Hence, chip designers scale down the process technology of the memories. The problem with process technology scaling would lower the standard operating voltage, conversely, due to the process variations, memory density increases. 4 Figure 2 shows the trends of industrial standard processors and SRAM memories with various operating voltages at different technology nodes presented in ISSCC. 3 Scaling the process technology node of SRAM memories is more sensitive to transistor variations. 5 This scaling also increases the soft error rate (SER). Ibe et al 6 discuss the SER of SRAM memories in 22 nm node rises by a factor of 7 as compared with 130 nm design. On the other hand, when an electronic component is subjected to radiation, its electrical properties change due to technology node scaling, large densities, and lower operating voltages. These exposures to radiation cause temporary or permanent system breakdown.Three distinct radiation environments are feasible to define, from earth's sea level to the planet's space orbit. They are terrestrial, atmospheric, and van Allen belt radiations. The National Aeronautical Space Administration (NASA) investigated spacecraft anomalies between 1974 and 1994 space missions. 7 Among those 100 various missions, it is clear that 35% and above of anomalies are caused to spacecraft failure due to the electronic component's radiation effects. So
