For next-generation wireless communications, the 3GPP Long Term Evolution-Advanced (LTE-A) is the most promising technology which provides transmission rate up to 1 Gbps and supports various broadband multimedia services, such as IPTV and Voice/Video-over-IP services. To reduce the energy consumption of user equipments (UEs), the LTE-A standard defines the Discontinuous Reception Mechanism (DRX) to allow UEs to turn off their radio interfaces and go to sleep when no data needs to be received. However, how to optimally configure DRX for UEs is still left as an open issue. In this paper, we address the DRX optimization problem for multicast services. This problem asks how to guarantee the quality of service (QoS) of the multicast streams under the Evolved Node B (eNB) while minimizing the UEs' wake-up time. We prove this problem to be NP-complete and propose an energy-efficient heuristic. This heuristic consists of two phases. The first phase tries to aggregate the required bandwidth of the multicast streams for UEs to reduce their wake-up periods. The second phase further minimizes UEs' unnecessary wake-up periods by optimizing their DRX configurations. Extensive simulation results show that our scheduling is close to the optimum in most cases.

This paper presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. Both simulation results and experimental results show great improvement in power consumption. A 256 8 delay buffer is fabricated and verified in 0.18 m CMOS technology and it dissipates only 2.56 mW when operating at 135 MHz from 1.8-V supply voltage.

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