Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or performance). The authors investigate systematic approaches to low-cost low-latency CED techniques for symmetric encryption algorithms based on inverse relationships that exist between encryption and decryption at algorithm level, round level, and operation level and develop CED architectures that explore tradeoffs among area overhead, performance penalty, and fault detection latency. The proposed techniques have been validated on FPGA implementations of Advanced Encryption Standard (AES) finalist 128-bit symmetric encryption algorithms.

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Here, we assume the construction of cyclic codes over ℜ={F}_{2}[u,v]/ < u^2, v^2 - v, uv - vu >. In particular, dual cyclic codes over ℜ= {F}_{2}[u]/ <u^2> with respect to Euclidean inner product are discussed. The cyclic dual codes over ℜ are studied with respect to DNA codes (reverse and reverse complement). Many interesting results are obtained. Some examples are also provided, which explain the main results. The GC-Content and DNA codes over ℜ are discussed. We summarise the article by giving a special DNA table.