The D-Algorithm (DALG) i s shown t o be i n e f f e c t i v e f o r t h e c l a s s o f combinational l o g i c c i r c u i t s t h a t i s used t o implement E r r o r C o r r e c t i o n and T r a n s l at i o n (ECAT) f u n c t i o n s . PODEM uses an i m p l i c i t enumeration approach analogous t o t h a t used f o r s o l v i n g 0 -1 i n t e g e r programming problems. PODEM ( P a t h -O r i e n t e d D e c i si o n Making) i s a new t e s t g e n e r a t i o n a l g o r i t h m I t i s shown t h a t PODEM i s very e f f i c i e n t f o r ECATc i r c u i t s and i s s i g n i f i c a n t l y more e f f i c i e n t than PODEM i s a complete a l g o r i t h m i n t h a t i t

Electronic Chip-in-Place Test (ECIPT) is a design approach and a test methodology for VLSI packages containing multiple semi-conductor chips.Shift register latches are used in such a way that each chip on a package is accessible for testing from the package pins without in-circuit probing. A means is therefore provided, whereby tests generated for a chip can be reapplied at the package level. The ECIPT methodology additionally provides a mechanism for simplified tests of failures associated with interchip wiring and chip I/O connections.19th Design Automation Conference 0420-0098/82/0000/0482500.75 © 1982 IEEE

Empirical observations are used to derive analytic formulae for test volumes, parallel fault simulation costs, deductive fault simulation costs, and minimum test pattern generation costs for LSSD logic structures.The formulae are significant in projecting growth trends for test volumes and various test generation costs with increasing gate count G.Empirical data is presented to support the thesis that test volume grows linearly with G for LSSD structures that cannot be partitioned into disjoint substructures.Such LSSD structures are referred to as "coupled" structures.Based on empirical observation that the number of latches in an LSSD logic structure is proportional to the gate count G, it is shown that the logic test time for coupled structures grows as G 2.It is also shown that (i) parallel fault simulation costs grow as G 3, (ii) deductive fault simulation costs grow as G 2, and (iii) the minimum test pattern generation costs grow as G 2.Based on these projections some future testing problems become apparent.Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery.To copy otherwise, or to republish, requires a fee and/or specific permission.

Multiple test generation algorithms and techniques described in this paper have been integrated into a unified system which has successfully produced tests for unpartitioned LSSD logic structures of up to 50,000 logic gates.The design concepts behind the creation of a unified system are presented, as are actual results obtained on large logic structures.System usability was significantly enhanced by the same concepts that facilitated the integration of multiple algorithms and techniques.