Electronic Chip-In-Place Test

Goel, Prabhakar; McMahon, Mark

doi:10.1109/dac.1982.1585542

Cited by 50 publications

(24 citation statements)

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“…The following results can be found in [10], [11], [13]; and they are divided according to the types of faults which are specifically targeted for diagnosis. 1) Short Faults: a unique Sequential Test Vector (STV) must be generated for each net [10] such that in absence of faults, the Sequential Response Vectors (SRV) or output patterns are still unique for all nets. For example, the Counting Sequence of [13] achieves fault detection using Parallel Test Vectors (PTV).…”

Section: Reviewmentioning

confidence: 99%

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Maximal diagnosis of interconnects of random access memories

et al. 2003

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This paper presents an approach for the maximal diagnosis of all faults (stuck-at, open and short) in the interconnect of a random access memory (RAM); and the interconnect includes data and address lines. This approach accomplishes maximal diagnosis under a complex model in which the lines in the interconnect of the RAM can be affected by multiple faults. Maximal diagnosis consists of detection and location of all diagnosable faults as well as type identification of multiple faults affecting each line. The proposed algorithm (referred to as the Improved Maximal Diagnosis Algorithm, or IMDA) requires max 1 + +3 WRITE and max +2 READ, where is the number of address lines and is the number of data lines. IMDA executes in three different steps: the first step diagnoses the data lines (and in particular the stuck-at faults); the second step accomplishes maximal diagnosis of the shorts (involving either the data lines only, or the data and address lines); and the third step completes the diagnosis of the address lines.

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Section: Reviewmentioning

confidence: 99%

“…Interconnect testing has recently experienced a rapid growth, and an extensive literature can be found [6], [7], [10], [11], [14], [17], [19]. These approaches can be differentiated by the conditions used for test pattern generation and the assumed fault model.…”

Section: Introductionmentioning

confidence: 99%

Maximal diagnosis of interconnects of random access memories

et al. 2003

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“…2) Boundary Scan: Boundary Scan uses special scan cells associated with the chip pins [130]. IBM has used LSSD-based boundary scan cells and associated test methodologies in practice at least since the early 1980s [131].…”

Section: ) Embedded Memory and Macro Testmentioning

confidence: 99%

EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

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“…Most previous work in testing interconnects focused on the development of deterministic tests for interconnect between chips at the board level [7,9,15,17,22,25,28]. As pointed out above, the extension of these board level methods to backplane testing is non-trivial.…”

Section: Introductionmentioning

confidence: 99%