We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

Epitaxial silicon nanowires ͑NWs͒ of short heights ͑ϳ280 nm͒ on Si ͗111͘ substrate were grown and doped in situ with boron on a concentration range of 10 15 -10 19 cm −3 by coevaporation of atomic Si and B by molecular beam epitaxy. Transmission electron microscopy revealed a single-crystalline structure of the NWs. Electrical measurements of the individual NWs confirmed the doping. However, the low doped ͑10 15 cm −3 ͒ and medium doped ͑3 ϫ 10 16 and 1 ϫ 10 17 cm −3 ͒ NWs were heavily depleted by the surface states while the high doped ͑10 18 and 10 19 cm −3 ͒ ones showed volume conductivities expected for the corresponding intended doping levels.

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We demonstrate a catalyst-free growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. To demonstrate the method single-crystalline InAs wires on Si as well as InAs-InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5-6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core-shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III-V based electronic and optoelectronic devices on silicon.

A method for determining charge carrier concentration, mobility, and relaxation time in semiconducting nanowires is presented. The method is based on measuring both the electrical conductivity and the Seebeck coefficient of the nanowire. With knowledge on the bandstructure of the material, Fermi level and charge carrier concentration can be deduced from the Seebeck coefficient. The ratio of measured conductivity and inferred charge carrier concentration then leads to the mobility, and using the Fermi level dependence of mobility one can finally obtain the relaxation time. Using this approach we exemplarily analyze the characteristics of an n-type InAs nanowire.