This paper presents a full custom memory layout design of 1KB SRAM, followed by physical verification checks, such as DRC and LVS to validate the layouts implemented. The Layout design technique such as device matching, routing matching, half-cell and symmetry has been followed carefully. The layouts were implemented using CADENCE EDA, Virtuoso platform was used for schematic and layout design. Assura physical verification environment was used for validating the layout designs. Technology nodes used are gpdk 180nm and 45nm. The full custom layout of 1KB SRAM architecture was successfully designed.