No abstract

The biggest challenge in the resistive random access memory (ReRAM) technology is that the basic operational parameters, such as the set and reset voltages, the current on-off ratios (hence the power), and their operational speeds, strongly depend on the active and electrode materials and their processing methods. Therefore, for its actual technological implementations, the unification of the operational parameters of the ReRAM devices appears to be a difficult task. In this letter, we show that by fabricating a resistive memory device in a thin film transistor configuration and thus applying an external gate bias, we can control the switching voltage very accurately. Taking partially reduced graphene oxide, the gate controllable switching is demonstrated, and the possible mechanisms are discussed.

Resistive Random Access Memory (ReRAM) has emerged as the successor to FLASH in memory technology due to its multi-level fabrication possibilities and prospects of scaling down virtually to atomic dimensions. However, as we report here, when polycrystalline switching materials are used, the ReRAM devices scaled down to the sub-5 nm2 area show complete randomness due to inhomogeneous conductance values of grains and grain boundaries. By measuring the switching properties of grains and grain boundaries individually using a scanning tunneling microscope, we demonstrate that the doublet and triplet grain boundaries behave like degenerate semiconductors and act as conduction channels that bypass the resistive switching of the devices. Fabricating virtual devices using gold clusters deposited on top, we show that the random distribution of such highly conducting grain boundaries reduces the reliability of nano-scale ReRAM devices when scaled down to the sub-10 nm scale.

This work elucidates the role of interface states of a metal-oxide-silicon device, the basic structure of CMOS integrated resistive random access memory (ReRAM) devices. By fabricating Au/Al2O3/Si ReRAM devices on silicon substrates oriented along ⟨100⟩ and ⟨111⟩ directions and employing the frequency dependence of capacitance and parallel conductance, we explore the role of interface trap densities (Dit) in the breakdown mechanism of ReRAM devices. In order to quantify the interface states, we measured the parallel conductance of the ReRAM devices as a function of frequency, which gives an accurate picture of the spread of Dit along the bandgap of silicon. Analysis of interface state density before and after the breakdown process reveals that the Si ⟨111⟩ surface is more prone to generate defects than Si ⟨100⟩ surfaces, and its elucidation is done by analyzing the pre-breakdown current behavior of the devices. Finally, the influence of the interface states on the thickness scaling is shown, where the thinner devices are inclined to have an earlier breakdown (Set voltage) due to the strong coupling with interface states.

In this paper, the authors showed a series of electromagnetic (EM) profiles (Figure 20, p. 86) obtained from the ground follow‐up using a slingram system with a frequency of 1600 Hz and coil separation of 120 m. Measurements along all the profiles (A to E) show considerable in‐phase and quadrature anomaly. The host rock in this case is amphibolite. The vertical electrical soundings over the amphibolite (Figure 16, p. 82) indicate that the weathered amphibolite has mean thickness and resistivity of 8.5 ± 2.1 m and 29.7 ± 6.5 Ω-m, respectively. It would, therefore, be reasonable to assume that the in‐phase and quadrature anomalies have been influenced due to the presence of conducting overburden, and the response of the target in such a situation can be altogether different compared to the anomaly of the target in the presence of an insulating or highly resistive overburden.