The proposed paper shows the half adder circuit with low power consumption preferred for arithmetic operations. Leakage power dissipation problem of electronics systems has attracted a lot of attention from engineers and researchers over the years. In the CMOS circuits Power dissipation occurs due to increasing leakage current in deep-sub micrometer regimes which is becoming a significant contributor as threshold voltage, channel length, and gate oxide thickness are reduced. The half adder circuit composed of XOR gate and AND logic gate, which have many transistor. Power consumption (leakage power) in the CMOS technology half adder circuit achieving better performance for maintain the speed, power dissipation, size, reliability of the device. SVL (Self-controllable Voltage Level) technique provides better leakage power reduction with minimum area and it not only reduces power but also retains data during stand-by period in half adder. Simulation work has been done in 45 nm technology, in this technology power consumption (leakage power) have provided for half adder circuit.

The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.

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