Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit

Abstract

The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.