Tunnel field-effect transistors (TFETs) are under intense investigation for low-power applications because of their potential for extremely low subthreshold swing (SS) and low off-state leakage [1]. III-V semiconductors with small effective mass and near broken band alignment are considered to be ideal for TFETs in that they promise high on-current and ION11oFF ratios [2][3]. In this paper, we report the first demonstration of an InAs/Alo.45Gao.55Sbheterojunction TFETs fabricated using an optical-lithography-only, self-aligned process and also investigate the effects limiting the InAsl Alo.45Gao.55Sb TFET performance. Fig. I(a) shows a cross section of the n-channel InAs/Alo.45Gao.55Sb TFET in a new tunneling geometry with the tunnel transport directed normal to the gate .. The TFETs were grown by molecular beam epitaxy (MBE) on a GaSb substrate. The epitaxial structure, starting from the substrate, consists of: 200 nmAISbl AlAs superlattice buffer layer, 300 nm of n+InAso9ISbo09,1O nm of n-InAs (Si-doped, 1 x 10 17 cm-\ 110 nm of p+GaSb, and 30 nm of p+AlxGal_xSb (Be-doped, 4 x 10 18 cm-3 ), with the Al composition x increased in three steps from 0 to 0.45, and concluding with a top 30 nm n-InAs layer (Si-doped, 1 x 10 17 cm-\ Three samples were processed; for one sample TFETs were fabricated on the heterostructures as grown, while in the other two the top InAs layer was thinned using Citric acid:H202 (1: 1) to 22 nm and 15 nm thickness, respectively. A 7 nm thick Ab03 gate dielectric was deposited by atomic layer deposition (ALD) immediately after cleaning in IHCI:IH20 for 30 s. A Ti/W/SiNx gate stack was blanket-deposited, then patterned using optical lithography, and reactive-ion etched (RIE). Plasma-enhanced chemical vapor deposition (PECVD) SiNx sidewalls were then formed around the gate, followed by removal of Ab03 gate dielectric using AZ 400K developer. After drain metallization and lift-off (Ti/Au), InAs was selectively etched in Icitric acid:IH202, followed by a selective AIGaSb etch using tartaric acid:H202:HCI:H20 (3.75 g : 4 ml : 40 ml : 400 ml) until the AIGaSb under the drain and the SiNx spacer was removed, forming the undercut mesa structure. Fig. I(b) shows the cross sectional image of a fabricated InAs/AIGaSb vertical TFET, taken after cross sectioning in a focused-ion beam and imaging by scanning electron microscopy (FIB/SEM). The SEM images clearly indicate that the InAsl AIGaSb tunnel junctions were fully overlapped by the gate electrode. Shown in Fig. 2 (a), (b) and (c) are the measured ID -VDS characteristics of a TFET with a 30 nm, 22 nm and 15 nm top InAs thickness at 300 K, respectively. The on-current is about 1200, 275 and 1 J.lA/�m at VDr 0.5 V, respectively, while the gate leakage is smaller than the drain current. The low on-current of the 15 nm InAs TFET is due to the overetching of the AIGaSb under the gate and consequent higher access resistance. Shown in Fig. 3(a) and (b) are the ID -VGS characteristics of TFETs with 22 nm and 15 nm of InAs at 300 K, respectively. While the dr...
