A low-noise and monolithic array tactile sensor, in which a tactile sensing unit, a low-noise analog front end (AFE), and a high-resolution delta-sigma analog-to-digital converter (ΔΣ ADC) are fully integrated, is presented in this paper. In this proposed system, compared with a discrete-device-based board-level system, the parasitic effect of a long cable connection can be reduced, and results are more accurate. Furthermore, a smaller system area and a lower power consumption can be achieved in this monolithic system. A discrete-continuous mixed mode bandpass AFE is proposed to filter out low-frequency flicker noise and high-frequency white noise. In order to improve the quantization rate of the sensor readout circuit and further suppress the high-frequency noise, a two-way alternate sample-and-hold circuit scheme is adopted in this design. The proposed tactile sensor is designed and fabricated in a 0.5-μm CMOS (Complementary metal oxide semiconductor)mixed-signal process with a 16 × 16 array and a total chip area of 1.9 × 1.9 cm2. This chip consumes 33.5 mW from a 5 V supply. The measurement results showed that the signal-to-noise and distortion rate (SNDR) was 65.2894 dB and that the effective number of bits (ENoB) was 10.553 dB. Moreover, this sensor could achieve a pressure measurement range of 0.002–0.5 N with a resolution of 0.4 mN.

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.

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