Development of SiGe HBTs in BiCMOS technology with both high f T and f MAX faces significant challenges. To increase f T, thinning the base and collector thickness is generally the first step to reduce the carrier transit times, but this increases the base resistance and the collector-base capacitance, which impacts f MAX negatively. Increasing collector doping is also often employed to increase f T, but this increases collector-base capacitance, which drives f MAX down. To overcome these limits, millisecond anneal techniques, low temperature silicide and low temperature contact processes are employed to reduce the base resistance. Concurrently a novel approach to reduce the extrinsic collector-base capacitance is developed, without affecting the manufacturability and integration with CMOS. The simultaneous reduction of both base resistance and collector capacitance enables high performance SiGe HBT devices in 90nm BiCMOS Technology with operating frequencies of 285/475GHz f T/f MAX.

Scaling silicon germanium heterojunction bipolar transistors (SiGe HBTs) to attain simultaneous increases in the figures of merit, fT and fMAX has necessitated a deep understanding of the inherent features of the process as it relates to the final device performance. Layout variations in the location of the field polysilicon layer relative to the edge of the active silicon region, results in marked changes in the intrinsic device, with increases in fT/fMAX of 15/20GHz respectively. Technology computer-aided device techniques are utilized to understand the process and device changes driving the improvements in device performance observed. Three possible theories that relate to changes in the device architecture inherent to the layout variation are examined.