The different equilibria in HF and HF/HCI solutions are examined and the etching reaction of SiQ is investigated as a function of the different species present in the HF solution. A new model for the etching mechanism of SiO~ is developed based on the existence of the dimer of HF, (HF)~.The dissolution of SiQ in HF solutions is a fundamental step in the fabrication of integrated circuits. Mat and Looney ~ have studied the etch rate of SiO2 in HF solutions as a function of the concentration, the temperature, the oxide growth process, and the stirring of the solution. The overall chemical reaction involved is normally understood as

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13µm CMOS process on 200mm wafers. The top die is thinned down to 25µm and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process. 3D-SIC processRecently 3D integration has gained a lot of interest due to its potential to alleviate some important performance limitations facing CMOS scaling and because it enables so-called heterogeneous integration [1][2]. Different approaches to 3D integration are reported depending on system level requirements [3]. Our 3D Stacked IC (3D-SIC) process [4][5] uses IC foundry infrastructure to create Through Silicon Vias (TSVs) prior to BEOL processing. The main advantage of this approach is the fact that it has minimal impact on both FEOL and BEOL design and processing. Furthermore it offers very high TSV densities. The TSV process sequence is summarized in Fig. 1. Figure 1: Schematic of the 3D-SIC Through Silicon Via (TSV) module.After processing of the CMOS FEOL and the PMD stack, we patterned TSVs with a diameter of 5µm and a pitch of 10µm using a 3µm thick I-line resist. We performed an undercut free, resist-based TSV etch (Fig. 2); undercut underneath the contact layer is avoided by pre-deposition of a polymer on the sidewall of the etched PMD/STI stack prior to the Si etch. For electrical isolation, we deposit a 100nm SACVD O 3 -TEOS layer. The metallization sequence consists of applying a 80nm PVD Ta barrier and a 300nm PVD Cu seed followed by an ECD via fill using a 3-component plating chemistry. Finally the Cu overburden is polished in a top-side TSV CMP step (Fig. 3). After this process, we apply a standard, 2 metal layer BEOL process to finalize the top Si-die. Figure 2&3: FIB through TSV in vicinity of device after etch, strip& clean (left), and after TSV CMP and sintering (right). (Pt on top for contrast).After wafer test, the wafer is mounted on a temporary carrier and thinned down to a Si-thickness of ~25 m by a combination of grinding and CMP. In this process, the TSVs are exposed on the wafer backside. Next the Si is recessed by dry etching over a distance of ~700nm with respect to the copper TSV. In this work the dies were then stacked by Cu-Cu thermo-compression bonding in a Die-to-Die (D2D) fashion, although compatibility with Die-to-Wafer integration remains. Figure 4 shows an optical 3D reconstruction of the obtained 3D stack. Figure 4: Optical 3D reconstruction based on multiple images at different height of thinned top die stacked to a bottom die by Cu-Cu bonding.

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We report on a major advancement in full-field EUV Lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186µm 2 6T-SRAMs, with W-filled contacts. Alignment to other 193nm immersion litho levels shows very good overlay values ≤20nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3σ≤7nm after double-dipole 193nm immersion litho (NA=0.85) and 3σ≤9nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM V DD scalability down to 0.6V (SNM>0.1V DD ) and healthy electrical characteristics (V T , σ(∆V T ), I-V) for the cell transistors are obtained.