We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated. Introduction Phase change memory (PCM) is widely considered to be a potential next-generation non-volatile solid-state memory [1-3]. In addition to its superior write speed compared to 0.2pm -flash, PCM offers a large signal margin between its -crystalline and amorphous states. This wide dynamic range Fig. 2: TEM image of phase-change element (PCE), with underlying also opens the door for multi-level cells (MLC). In this paper, TiN heater on top of W contact. The phase-change material and the we explore MLC write algorithms for up to 16 levels in small o T test arrays, and then demonstrate a 4-level, 32kbit page being overln Tiner are coNnected ubinEs thr a via.part of an experimental memory chip. transferred into the TiN layer using RIB. After strip, oxide isolation is deposited and planarized, exposing the top of the Integration Scheme pillar electrode. The Ge2Sb2Te5 and TiN top electrode layers The memory cell consists of a pillar-heater phase change are then deposited, patterned into islands and encapsulated element (PCE) in series with an access nMOSFET (180nm with dielectric. Top contacts and metallization lines are CMOS technology). As shown in Fig. 1, the 50nm bottom formed using a standard Cu damascene process. Fig. 2 shows electrode heater is fabricated in a subtractive process from a a TEM cross-section of the finished pillar-heater PCE. 75nm thick TiN layer directly deposited over the W contacts.

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with <100µA RESET current. The device concept provides for simplified scaling to small crosssectional area (60nm 2 ) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention.

The memory capacity, computational power, communication bandwidth, energy consumption, and physical size of the brain all tend to scale with the number of synapses, which outnumber neurons by a factor of 10,000. Although progress in cortical simulations using modern digital computers has been rapid, the essential disparity between the classical von Neumann computer architecture and the computational fabric of the nervous system makes large-scale simulations expensive, power hungry, and time consuming. Over the last three decades, CMOS-based neuromorphic implementations of “electronic cortex” have emerged as an energy efficient alternative for modeling neuronal behavior. However, the key ingredient for electronic implementation of any self-learning system—programmable, plastic Hebbian synapses scalable to biological densities—has remained elusive. We demonstrate the viability of implementing such electronic synapses using nanoscale phase change devices. We introduce novel programming schemes for modulation of device conductance to closely mimic the phenomenon of Spike Timing Dependent Plasticity (STDP) observed biologically, and verify through simulations that such plastic phase change devices should support simple correlative learning in networks of spiking neurons. Our devices, when arranged in a crossbar array architecture, could enable the development of synaptronic systems that approach the density (∼10 11 synapses per sq cm) and energy efficiency (consuming ∼1pJ per synaptic programming event) of the human brain.

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