A multiplying delay-locked loop (MDLL) for highspeed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-m CMOS technology, occupies a total of 0.05 mm 2 of active area and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of = 4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72 72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk). IndexTerms-Clock multiplication, clock synthesis, delay-locked loop (DLL), low jitter, phase-locked loop (PLL), serial links.

Index Terms-Clock recovery, multi-level signaling, receiver equalizer networks, serial links.

Abstract-This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a firstorder DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filtering and phase filtering are discussed. Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated.Index Terms-Delay-locked loop (DLL), injection locking, jitter peaking, jitter transfer, multiplying delay-locked loop (MDLL), phase-locked loop (PLL).

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