A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

Abstract

A multiplying delay-locked loop (MDLL) for highspeed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-m CMOS technology, occupies a total of 0.05 mm 2 of active area and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of = 4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72 72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk). IndexTerms-Clock multiplication, clock synthesis, delay-locked loop (DLL), low jitter, phase-locked loop (PLL), serial links.

A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier

“…Unlike the conventional MDLL [3] that has a harmonic locking problem, the proposed MDLL utilizes a simple harmonic lock detector to avoid harmonic locking. As shown in Fig.…”

“…Recently, multiplying delay-locked loop (MDLL) [3,4] based frequency multipliers have been introduced to replace PLL-based ones due to their advantages such as ease of design, smaller area, lower power dissipation, nostability issue, and better jitter performance. However, conventional MDLLs [3,4] suffer from a harmonic locking problem.…”

“…However, conventional MDLLs [3,4] suffer from a harmonic locking problem. Harmonic locking occurs when the DLL and MDLL locks to harmonic reference edges of the input clock as shown in Fig.…”

A 2–4 GHz fast-locking frequency multiplying delay-locked loop

“…In recent years, multiplying delay-locked loops (MDLLs) [5,6,7,8,9, 10, 11] have been introduced as an alternative to conventional PLLs [1,2,3,4]. An MDLL achieves better phase noise performance by periodically injecting a clean reference input clock to the delay line [5,6,7,8]. MDLLs can generate integer-ratio [5,6,7,8,9,10,11] or fractional-ratio [12, 13] frequency multiplication.…”

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider

“…Compared with the PLL based clock generator, this implementation is easier to design but multiplication ratio is fixed and the mismatches in the delay stages and edge-combining logic significantly contributes the output deterministic timing jitter. So recently more efforts are taken on obtaining the programmable multiplication ratios and avoiding mismatches [3] [4]. This paper describes a DLL based clock generator with a dynamic frequency divider to achieve a programmable frequency ratio and low phase noise.…”