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This paper compares the performance and inter-die variability of doped and undoped channel Multiple-Gate FETs (MUGFETs) with respect to planar SOI devices. We show that doped-channel FinFETs have equivalent variability to narrowwidth planar devices. As such, transitions to FinFETs for narrow-width devices will likely incur minimal variability impact. To match the low variability of wide-width planar devices, conversions to undoped channel FinFETs will be necessary. Furthermore, good short-channel control has to be maintained since undoped channel devices exhibit increase sensitivity to T body relative to doped channel FinFETs due to enhanced fully-depleted channel electrostatics.

SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product's lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (V T ) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor V T has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues. IntroductionSRAM reliability on sub-65nm nodes has become a significant challenge. Transistor mis-match at time zero, as well as over the lifetime of a product, could result on memory fails. The screening techniques used to date count on failure mechanisms being present at time zero in order for them to be screened, or they attempt to guard-band products with ranges large enough to contain forecasted shifts. This paper presents a methodology developed on 65nm low power and high performance process technologies at Texas Instruments that is able to screen memory cells that are likely to have stability issues over the lifetime of a product.

BEOL yield characterization is increasingly difficult on advanced technology nodes using traditional short flow devices. A new BEOL Technology Development Read Only Memory (TDROM")' has been used to successfully drive BEOL yield learning on the 65 nm node. The addressable nature of the TDROM"^ allows isolation of all fails to within 2 um2 using known memory testing techniques which has resulted in accelerated yield learning, and PFA utilization. The eight megabit array size allows exhaustive DOE'S for all design rules and margins.