A Screening Methodology for VMIN Drift in SRAM Arrays with Application to Sub-65nm Nodes

Abstract

SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product's lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (V T ) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor V T has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues. IntroductionSRAM reliability on sub-65nm nodes has become a significant challenge. Transistor mis-match at time zero, as well as over the lifetime of a product, could result on memory fails. The screening techniques used to date count on failure mechanisms being present at time zero in order for them to be screened, or they attempt to guard-band products with ranges large enough to contain forecasted shifts. This paper presents a methodology developed on 65nm low power and high performance process technologies at Texas Instruments that is able to screen memory cells that are likely to have stability issues over the lifetime of a product.

Characterization of Dynamic SRAM Stability in 45 nm CMOS

“…These marginal transistors did not degrade static write margin due to the negligible sensitivity of the margin to variability in (Table I). Voltage screen tests such as described in [16] are commonly used to screen out defects and early failures in SRAM arrays. Such tests are usually carried out in-line at wafer sort using testers running at lower frequencies than actual operating frequencies.…”

An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of ${\rm V} _{\rm MIN}$ Degradation

“…Flipping SRAM cell data periodically removes stress and recovers the degraded SNM. Ball et al [17] developed a screening methodology for drift in SRAM arrays. Measured results showed that NWELL body bias control increases the likelihood of fails coming from lowered SNM.…”

SRAM Redundancy - Silicon Area versus Number of Repairs Trade-off

“…Vmin fails have become the dominant memory fail mechanism throughout the product life cycle [1,2]. To maintain acceptable yields added SRAM redundancy is recommended.…”