An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of ${\rm V} _{\rm MIN}$ Degradation

Abstract

Negative bias temperature instability (NBTI) has been considered as a main reliability issue in SRAMs since the threshold voltage degradation of PMOS transistors due to NBTI has raised minimum operating voltage (V MIN ) over time. This paper explains an SRAM reliability test macro designed in a 1.2 V, 65 nm CMOS process technology for statistical measurements of V MIN degradation coming from NBTI. An automated test program efficiently collects statistical V MIN data and reduces test time. The proposed test structure enables V MIN degradation measurements for different SRAM failure modes such as the SNM-limited case and the access-time-limited case. The V MIN dependency on initial device mismatch and stored data is also presented. The measured time to cell data flip affected by NBTI shows the similar trend of NBTI following a power-law dependency on stress time. Index Terms-Circuit reliability, minimum operating voltage (V MIN ), negative bias temperature instability (NBTI), static random access memory (SRAM).

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

“…On the other hand, to keep the memory functioning and maintain the data at hold mode, memory designers usually consider performing some tests during the memory lifetime and increase the standby supply voltage [19]. Increasing the supply voltage step by step improves the hold SNMs and keeps the memory functional at lower voltages than active supply voltage.…”

Impact Analysis of NBTI/PBTI on SRAM VMINand Design Techniques for Improved SRAM VMIN

“…As the SNM becomes more negative, the speed of the data-flip becomes higher [6]. This is because the more negative SNM provides larger voltage disturbance into the cell nodes and the positive feedback of the cross-coupled inverters amplifies it faster.…”

“…A number of works have dealt with the impact of NBTI and PBTI on SRAM operation [3][4][5][6]. The threshold voltage degradation due to NBTI and PBTI decreases cell stability, which will become even more serious when combined with device mismatches [5,6].…”

“…The threshold voltage degradation due to NBTI and PBTI decreases cell stability, which will become even more serious when combined with device mismatches [5,6]. Li et al analyzed the impact of NBTI on SRAM cell operation and claimed that the NBTI in an SRAM cell has a stronger impact on read and write speed than on static noise margin (SNM) particularly when the clock frequency is high [7].…”

Circuit level technique for mitigating effects of NBTI for wide fan-in domino logic circuits using supply voltage tuning

“…When stress is removed, it starts the recovery phase wherein the trapped holes are released and the diffused Hydrogen atoms, diffuse back to the Si-interface [ Fig. 1(b)] [1]. Due to hole de-trapping in the gate-oxide [2], upon removal of the negative stress there is an immediate partial recovery from the threshold shift that occurred during stress.…”