The ability of graphene to transduce an adsorption event of ions into a detectable electrical signal has sparked a lot of interest for its use in sensors. However, a low concentration of the chemically active sites for binding analytes on the graphene surface has significantly prevented its applications so far. Here, we report on implementation of the van der Waals heterostructure based on a monolayer graphene and an ∼1-nm-thick molecular carbon nanomembrane (CNM) in a solution-gated field-effect transistor (FET) for pH sensing. The nondestructive functionalization of a graphene FET with the amino-terminated CNM (NH2-CNM) enables the induction of chemically active groups in the vicinity of the graphene sheet, maintaining its charge carrier transport properties. We applied complementary characterization techniques, including Raman spectroscopy, x-ray photoelectron spectroscopy, and optical and atomic force microscopy as well as field-effect and electrical impedance measurements to characterize the engineered NH2-CNM/graphene devices. We demonstrate their high pH resolution with a minimum detectable pH change of ∼0.01 at pH 2 and ∼0.04 at pH 12, with a response time in the range of seconds, and we apply an electrical double-layer model to rationalize the experimentally observed performance theoretically. The developed device concept enables the engineering of microscale pH sensors for applications in biological and environmental sciences.

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing with potential for low cost applications. Wafer level embedding technologies and embedding of active components into printed circuit boards CChip-in-Polymer) are two major packaging trends in this area. This paper describes the use of compression and transfer molding techniques for multi chip embedding in combination with large area and low cost redistribution technology from printed circuit board manufacturing as adapted for Chip-in-Polymer applications. The work presented is part of the German governmental funded project SmartSense. Embedding by transfer molding is a well known process for component embedding that is widely used for high reliable microelectronics encapsulation. However, due to material flow restrictions transfer molding does not allow large area encapsulation, but offers a cost effecti ve technology for embedding on a medium size scale as known e.g. from MAP Cmolded array packaging) molding Ctypically with sizes up to 60×60 mm2). In contrast, compression molding is a relatively new technology that has been especially developed for large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically up to 8" or even up to 12". Wiring of these embedded components is done using PCB manufacturing technologies, i.e. a resin coated copper CRCC) film is laminated over the embedded components - no matter which shape the embedded components areas are: a compression molded wafer, larger rectangular areas or smaller transfer molded systems CMAP). Typical process flow for RCC redistribution is lamination of RCC, via drilling to die pads by laser, galvanic Cu via filling, conductor line and pad formation by Cu etching, soldermask and solderable surface finish application - all of them standard PCB processes. The feasibility of the technology is de

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12"/300 mm diameter. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 24"×18" or even larger. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. As a process alternative also lamination as used e.g. in PCB manufacturing can be taken into account.=Within this paper the evaluation of panel level compression molding with a target form factor of 24”*18” / 610×457 mm2 is described. The large panel size equals a typical PCB manufacturing full format and is selected to achieve process compatibility with cost efficient PCB processes. Here not only conventional compression molding is considered but also the new process compression mold lamination is introduced as a tool-less mold alternative. Panel level molding is compared to 8” and 12” wafer molding as well as to low cost PCB 24”×18” lamination focusing on manufacturing challenges, high volume capability and estimated cost. Technological focus of this study will be the evaluation of liquid, granular and sheet molding compound. This includes thorough material analysis regarding the process relevant material properties as reactivity or viscosity. One key process step for homogeneous large area embedding is material application before compression molding. Where sheet compounds already deliver a uniform material layer the application of liquid and granular compound must - e optimized and adapted for a homogeneous distribution without flow marks, knit lines and incomplete fills. Hence, dispense patterns of liquid and granular molding compounds are studied to achieve high yield and reliable mold embedding. In addition applicable thickness ranges, total thickness variations, void risks and warpage will be investigated for the different material types. The overall a process flow will be demonstrated for selected compression mold variants resulting in a 24”×18” / 610×457 mm2 FOPLP using PCB based redistribution layer (RDL) as low cost alternative to thin film technology. For=PCB based RDLs a resin coated copper sheet (RCC) is laminated on the reconfigured wafer or panel, respectively. Micro vias are drilled through the RCC layer to the die pads and electrically connected by Cu plating. Final process step is the etching of Cu lines using laser direct imaging (LDI) techniques for maskless patterning. All process steps are carried out on full format 24”×18” / 610×457 mm2

The constant drive towards further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of a novel S2iP (Stacked System in Package) interconnect technique using advanced molding process for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically 8” to 12”. Future developments will deal with panel sizes up to 470 × 370 mm2. The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - whichever no matter which shape they are: a compression molded wafer or a larger rectangular area of a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating - all of them making use of standard PCB processes. Thus, through vias which are standard features in PCB manufacturing and can be also integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. Vias were drilled by laser or mechanically after RCC lamination and were metalized together with the vias for chip interconnection. Within this study different liquid and granular moldi- - ng compounds have been intensively evaluated on their processability. Via drilling process by laser and mechanical drilling is systematically developed and analyzed with focus on via diameter, pitch, mold thickness and molding compound composition and here especially on filler particle sizes and distribution. The feasibility of the entire process chain is demonstrated by fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. Finally, a technology demonstrator is described consisting of two BGAs stacked on each other and mounted on a base substrate enabling the electrical test of a daisy chain structure through the stacked module, allowing the evaluation of the technology and the applied processes

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