The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing with potential for low cost applications. Wafer level embedding technologies and embedding of active components into printed circuit boards CChip-in-Polymer) are two major packaging trends in this area. This paper describes the use of compression and transfer molding techniques for multi chip embedding in combination with large area and low cost redistribution technology from printed circuit board manufacturing as adapted for Chip-in-Polymer applications. The work presented is part of the German governmental funded project SmartSense. Embedding by transfer molding is a well known process for component embedding that is widely used for high reliable microelectronics encapsulation. However, due to material flow restrictions transfer molding does not allow large area encapsulation, but offers a cost effecti ve technology for embedding on a medium size scale as known e.g. from MAP Cmolded array packaging) molding Ctypically with sizes up to 60×60 mm2). In contrast, compression molding is a relatively new technology that has been especially developed for large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically up to 8" or even up to 12". Wiring of these embedded components is done using PCB manufacturing technologies, i.e. a resin coated copper CRCC) film is laminated over the embedded components - no matter which shape the embedded components areas are: a compression molded wafer, larger rectangular areas or smaller transfer molded systems CMAP). Typical process flow for RCC redistribution is lamination of RCC, via drilling to die pads by laser, galvanic Cu via filling, conductor line and pad formation by Cu etching, soldermask and solderable surface finish application - all of them standard PCB processes. The feasibility of the technology is de

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Together with the Kirchhoff-Institute for Physics the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the Kirchhoff-Institute for Physics and the associated hardware requirements which drove the described technological developments.In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a high density reticle-to-reticle routing on 200 mm CMOS wafers. Neighboring reticles were interconnected across the scribe lines with an 8 µm pitch routing based on semi-additive copper metallization which was photo defined by full field mask aligning equipment. Passivation by photo sensitive benzocyclobutene (BCB) was used to enable a second intra-reticle routing layer. Final IO pads of nickel with flash gold were generated on top of each reticle. For final electrical connection the wafers were placed into mechanical fixtures and the IOs of all reticles were touched by elastomeric connectors. With that concept neuromorphic systems based on full wafers could be assembled and tested. The fabricated high density inter-reticle routing revealed a very high yield of larger than 99.9 %.In order to allow an upscaling of the system size to a large number of wafers with feasible effort a full wafer embedding concept for printed circuit boards was developed and proven in the second phase of the project. The wafers were thinned to 250 µm and laminated with additional prepreg layers and copper foils into a core material. A 200 mm circular cut was done into the core material and the inner prepreg layers to create the required clearance for the wafer. After lamination of the PCB panel the reticle IOs of the embedded wafer were accessed by micro via drilling, copper electroplating, lithography and subtractive etching of the PCB wiring structure.The created wiring with 50 µm line width enabled an access of the reticle IOs on the embedded wafer as well as a board level routing. The panels with the embedded wafers were subsequently stressed with up to 1000 thermal cycles between 0 °C and 100 °C and have shown no severe failure formation over the cycle time.

Assembly of electronic components on rigid and/or flexible printed circuit boards is today the customary way to fabricate electronic systems in stationary, mobile and automotive applications. On the other hand, many of the demands from emerging application fields like wearable and textile electronics cannot be met if with standard technologies. These fields have therefore become mayor drivers for the development of novel technologies. Among these "stretchable electronics" have attracted much attention recently. Especially for textile applications the potential of the electronic system to comply with the body shape and movement will considerably improve the user comfort. The paper presents a cost effective technology for the realization of stretchable systems by common printed circuit board techniques with polyurethane as a stretchable matrix material. Mastering of the adhesion between materials and the transitions region from stretchable to non-stretchable parts of the system are crucial for the mechanical performance and robustness. Technical approaches and the obtained results to tackle these issues are presented. The described process technology bears the potential for large scale roll to roll processing. Reliability aspects for stretchable electronic systems are so far not standardized and will be discussed briefly. Electrical and mechanical functionality of test vehicles subjected to multiple stretch and mild washing cycles will be presented. A functional electronic demonstrator with embedded passives, a micro controller, and LEDs which was realized with this technology is shown

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