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This paper presents a FPGA and DSP based high-speed multiplexed 24 channel bus architecture. The new bus architecture is a modified version of the existing multi-core processor architecture and distributed architecture to meet multichannel and multi processor requirement. Design includes implementation of constrained multiplexing, controlling and routing algorithm for packet data transfer at the rate of 256Mbps using external FIFO. The system uses a simplified time division multiplexing and data interleaving for high speed data congestion avoidance and error correction and incorporate an adaptive architecture for switching between FPGA and DSP for data transfer using a single shared high speed parallel bus (signed fixed point) and distributed control lines. Communication control for FPGA data processing is via DSP utilizing serial interface. The architecture reduces global clocking resources for FPGA implementation making the system simple and reduces dynamic power consumption. The design blocks are modeled using VHDL and implemented in Spartan 3A DSP FPGA using finite state machine, improving data path timing to manage high speed data traffic and to achieve error free data communication with external systems.

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In this paper we focused on to reduce the latency time for 5G applications using hardware accelerator. In current 4G systems the roundtrip latency period is about 15mS, The 5G applications will need a roundtrip latency period less than about 1 ms, faster than 4G.The latency constraints may have major role in the design of a 5G communication system. 5G networks will require tight inter-coordination between multiple network elements and tight sharing of spectrum.OFDMA can only operate if strict time and frequency synchronization between users and a base station is achieved. There is a need for a filtered, multicarrier approach with reduced side-lobe levels of the waveform which could minimize inter-carrier interference (ICI) in 5G, FBMC (filter bank multi-carrier) generalizes traditional orthogonal frequency-division multiplexing (OFDM) schemes. The proposed work consists of latency analysis of filter bank based multicarrier (FBMC) transmitter and receiver with and without a hardware accelerator. This waveform is a possible candidate for 5G. The result of this experiment will be one of the references to finalize engineering requirements of 5G wireless communication system in terms of latency.