This paper presents a FPGA and DSP based high-speed multiplexed 24 channel bus architecture. The new bus architecture is a modified version of the existing multi-core processor architecture and distributed architecture to meet multichannel and multi processor requirement. Design includes implementation of constrained multiplexing, controlling and routing algorithm for packet data transfer at the rate of 256Mbps using external FIFO. The system uses a simplified time division multiplexing and data interleaving for high speed data congestion avoidance and error correction and incorporate an adaptive architecture for switching between FPGA and DSP for data transfer using a single shared high speed parallel bus (signed fixed point) and distributed control lines. Communication control for FPGA data processing is via DSP utilizing serial interface. The architecture reduces global clocking resources for FPGA implementation making the system simple and reduces dynamic power consumption. The design blocks are modeled using VHDL and implemented in Spartan 3A DSP FPGA using finite state machine, improving data path timing to manage high speed data traffic and to achieve error free data communication with external systems.