Massively parallel computer systems based on off-theshelf CPU chip-sets hate become commercially available [Think9I,Intel91]. We demonstrate a theoretical limit on the silicon (or other circuitry media) utilization of such architectures as the number of processors is scaled up. In addition, case studies of the Thinking Machines Corporation CM-5@ and of the Intel Touchstone8 are presented in order to quantify the maximum utilization on existing machines. Based on this utilization limit, we examine whether computer architects' current reliance on the MIMD model will be practical in next generation machines. In order to facilitate the analysis, we decouple the control parallel and data parallel models of computation from MIMD and SIMD target plarfom. respectively [Siege187,Dietz92, Hu&k88]. Utilization of control parallel paradigms executing on SIMD platforms is introduced for comparison purposes [Dutz92]. We also consider the relationship of communication overhead to machine size scaling in the presence of the need for virtual processing nodes.

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