A CPU utilization limit for massively parallel MIMD computers

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

Hoare

Kusic

et al. 2005

The capability and heterogeneity of new FPGA (Field Programmable Gate Array) devices continues to increase with each new line of devices. Efficiently programming these devices is increasing in difficulty. However, FPGAs continue to be utilized for algorithms traditionally targeted to embedded DSP microprocessors such as signal and image processing applications.This paper presents an architecture that combines VLIW (Very Large Instruction Word) processing with the capability to introduce application specific customized instructions and complex hardware functions. To support this architecture, a compilation and design automation flow are described for programs written in C.Several design tradeoffs for the architecture were examined including number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply accumulate operations.We show that our combined VLIW with hardware functions exhibit as much as 230X speedup and 63X on average for computational kernels for a set of benchmarks. This allows for an overall speedup of 30X and 12X on average for signal processing benchmarks from the MediaBench.

“…Coprocessor arrays have been studied for their impact on speech coders [8] [9], video encoders [10] [11], and general vector-based signal processing [12][13] [14].…”

Section: Related Workmentioning

confidence: 99%

An FPGA-based VLIW processor with custom hardware execution

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

Hoare

Kusic

et al. 2005

“…Many SuperCISC functions can be combined on a single chip to exploit an even higher degree of parallelism. Due to the iterative nature of most vectorbased signal processing applications, the utilization of coprocessors has been investigated extensively [15]. Replication of hardware functions can be used to unroll time consuming loops and observe greater amounts of speedup.…”

Section: Kernel Replication Vs Pipeliningmentioning

confidence: 99%

Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions

Ihrig

Stander

2007 IEEE International Parallel and Distributed Processing Symposium

2007

“…The support of custom instructions for interface with coprocessor arrays and CPU peripherals has developed into a standard feature of soft-core processors and those which are designed for DSP and multimedia applications. Coprocessor arrays have been studied for their impact on speech coders [25,26], video encoders [27,28], and general vector-based signal processing [29][30][31].…”

Section: Related Workmentioning

confidence: 99%

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions

Hoare

EURASIP J. Adv. Signal Process.

Kusic

et al. 2006

This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1) a 4-way VLIW processor implemented in an FPGA, (2) large speedups through hardware functions, (3) a hardware/software interface with zero overhead, (4) a design methodology for implementing signal processing applications on this architecture, (5) tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to 230 times that of software with an average 63 times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.