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A new trench-capacitor DRAM cell has been recently demonstrated in an advanced, 3 . 3 volt n-well CMOS technology with fabrication of functional, fully-decoded 64K arrays.

A 33-ns 64-Mb DRAM with a master-wordline architecture that allows for wordline boosting has been successfully designed and fabricated. The master-wordline scheme incorporates a high-threshold PFET which enables the boost voltage to be controlled by standard CMOS levels. The high-threshold PFET also generates a stable low-power reference voltage for the boost system.

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