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The Altera Cyclone family of FPGA provides the ability to perform run time reconfiguration which is known as Dynamic Reconfiguration. This paper concentrates on how to take a complex System-on-Chip design into three different components: fixed hardware, reconfigurable hardware and software, each handled by dedicated sub flow. The method to dynamically reconfigure the pll and application used to see variations in frame rate using LCD Display Controller with FPGA is presented. This flow can be considered a part of a general methodology that can be exploited for the implementation on a complex System on Programmable Chip. An example of application it consists utilizes the reconfigurable clocks generated by PLL and video processing in the reconfigurable module. The architecture of the proposed application will presented in this paper were prototyped using a Cyclone III Starter Board, which is based on Nios II Embedded Evaluation Kit, Cyclone III Edition.

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