Pressure fluctuations are a critical phenomenon that can endanger the safety and stability of hydraulic structures, especially stilling basins. Hence, the accurate estimation of the dimensionless coefficient of pressure fluctuations ( C P ′ ) is critical for hydraulic engineers. This study proposed predictive soft computing models to estimate C P ′ on sloping channels. Therefore, three robust soft computing methods, including extreme learning machine (ELM), group method data of handling (GMDH), and M5 model tree (M5MT), were used to estimate C P ′ . The results revealed that ELM was more accurate than GMDH and M5MT methods when comparing statistical indices, including correlation coefficient (CC), root mean square error (RMSE), mean absolute error (MAE), scatter index (SI), index agreement ( I a ), and BIAS values. The performance of ELM was found to be more accurate (CC = 0.9183, RMSE = 0.0067, MAE = 0.0051, SI = 11.88%, Ia = 0.9569) when compared with the results of GMDH (CC = 0.8818, RMSE = 0.0078, MAE = 0.0058, SI = 13.89%, Ia = 0.9361) and M5MT (CC = 0.6883, RMSE = 0.0120, MAE = 0.0090, SI = 21.28%, Ia = 0.7905) in the testing stage. In addition, the BIAS values revealed that ELM slightly overestimated the values of C P ′ , especially at the peak point compared with GMDH and M5MT results. Overall, the suggested soft computing techniques worked well for predicting pressure fluctuation changes in the hydraulic jump.

<p>The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.</p>