Al/Cs/MDMO-PPV/ITO "where MDMO-PPV stands for poly͓2-methoxy-5-(3Ј-7Ј-dimethyloctyloxy͒-1,4-phenylene vinylene͔ and ITO is indium tin oxide… light-emitting diode ͑LED͒ structures, made by physical vapor deposition of Cs on the emissive polymer layer, have been characterized by electroluminescence, current-voltage, and admittance spectroscopy. Deposition of Cs is found to improve the balance between electron and hole currents, enhancing the external electroluminescence efficiency from 0.01 cd A Ϫ1 for the bare Al cathode to a maximum of 1.3 cd A Ϫ1 for a Cs coverage of only 1.5ϫ10 14 atoms/cm 2 . By combining I-V and admittance spectra with model calculations, in which Cs diffusion profiles are explicitly taken into account, this effect could be attributed to a potential drop at the cathode interface due to a Cs-induced electron donor level 0.61 eV below the lowest unoccupied molecular orbital. In addition, the admittance spectra in the hole-dominated regime are shown to result from space-charge-limited conduction combined with charge relaxation in trap levels. This description allows us to directly determine the carrier mobility, even in the presence of traps. In contrast to recent literature, we demonstrate that there is no need to include dispersive transport in the description of the carrier mobility to explain the excess capacitance that is typically observed in admittance spectra of -conjugated materials.

RF circuit design in deep-submicrometer CMOS technologies relies heavily on accurate modeling of thermal noise. Based on Nyquist's law, predictive modeling of thermal noise in MOSFETs was possible for a long time, provided that parasitic resistances and short-channel effects were properly accounted for. In sub-100-nm technologies, however, microscopic excess noise starts to play a significant role and its incorporation in thermal noise models is unavoidable. Here, we will review several crucial ingredients for accurate RF noise modeling, with emphasis on sub-100-nm technologies. In particular, a detailed derivation and discussion are presented of our microscopic excess noise model. It is shown to qualitatively explain the observed noise (across bias and geometry) in a wide range of commercially available sub-100-nm foundry processes. Besides, the impact of excess noise on the minimum noise figure is discussed.

In this paper, it is shown that self-heating causes a gigantic effect on the capacitances of MOSFETs/FinFETs. The effect is used to determine the SOI FinFET thermal impedance and to determine the temperature rise during FinFET operation. IntroductionFinFETs are regarded as prospective replacements for bulk-CMOS devices beyond the 22-nm node. Due to the poor thermal conductivity of some of the materials used in FinFET fabrication, and due to the confined nature of the FinFET geometry, self-heating is expected to be more significant in FinFETs than in their bulk-CMOS counterparts, affecting not only device performance, but also NBTI and oxide reliability [1,2]. To the best of the authors' knowledge, all studies on FinFET self-heating so far are based on simulations [1,3,4], and experimental assessment is lacking. In this paper, we will (i) show that self-heating causes a gigantic effect on the capacitances C DD and C DG , (ii) use that effect as an ultra-sensitive method to extract the frequency-dependent complex thermal impedance Z th (f ), and (iii) determine the temperature rise in our SOI FinFETs and its impact on the device performance.

We present a new, PSP-based compact model for symmetric 3-terminal FinFETs with thin undoped or lightly doped body, which is suitable for digital, analog and RF circuit simulation. The model is surface potential based and is demonstrated to accurately describe both TCAD data and measured FinFET currents, conductances, and capacitances

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