Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes

Tiemeijer, L.F.; Pijper, Ralf; Havens, R.J.; Hubert, O.

doi:10.1109/tmtt.2007.891691

Cited by 46 publications

(16 citation statements)

References 20 publications

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“…3), allowing the fully differential transceiver design and reducing crosstalk between adjacent transmission lines. The transmission lines utilize the patterned ground shield to reduce the substrate loss by preventing the electric field from penetrating the substrate [12].…”

Section: Chip Prototype Designmentioning

confidence: 99%

A 25-Gbps 8-ps/mm transmission line based interconnect for on-chip communications in multi-core chips

Huang

2013

2013 IEEE MTT-S International Microwave Symposium Digest (MTT)

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This paper presents a novel on-chip interconnect system for multi-core chips using transmission lines as shared media. It supports both point-to-point and broadcasting communications. Compared to network-on-chip approaches, it offers significant advantages in circuit complexity, energy efficiency and link latency. To demonstrate the scheme, a chip prototype with two 20-mm long transmission lines running in parallel and multiple transmitters/receivers (including 2:1 serializer/1:2 deserializer) was implemented in a 130-nm SiGe BiCMOS technology. The prototype can achieve a date rate of 25.4 Gb/s with an energy efficiency of 1.67 pJ/b in the measurement.

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Section: Chip Prototype Designmentioning

confidence: 99%

A 25-Gbps 8-ps/mm transmission line based interconnect for on-chip communications in multi-core chips

Huang

2013

2013 IEEE MTT-S International Microwave Symposium Digest (MTT)

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“…Unlike physical models where the transmission line parameters are correlated with the physical structure, the nonphysical models are extracted directly from the frequency response and, therefore, do not relate to the physical structure of the transmission line. Afterward, efforts have been put into developing analytical expressions for the shielded transmission lines inductances to describe key performance figures with a good accuracy (Tiemeijer et al, 2007;Masuda et al, 2008). In (Wang et al, 2008), the authors tried to go further by calculating the inductance and the resistance of the shielded coplanar waveguides using the partial element equivalent circuits (PEEC) method.…”

Section: State Of the Artmentioning

confidence: 99%

Integrated Silicon Microwave and Millimeterwave Passive Components and Functions

Benech¹,

Duchamp²,

Ferrari³

et al. 2010

Microwave and Millimeter Wave Technologies From Photonic Bandgap Devices to Antenna and Applications

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“…Figure 6 shows the measurement results of the transmission line. The measurement procedure is similar to [10]. The transmission line has a differential impedance of 100Ω and an attenuation of 1.3dB/mm at 60GHz.…”

Section: Lnamentioning

confidence: 99%

A 60GHz digitally controlled phase shifter in CMOS

Baltus

Roermund

et al. 2008

ESSCIRC 2008 - 34th European Solid-State Circuits Conference

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Abstract-This paper presents a 60GHz digitally controlled phase shifter in the 65nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5°, an average insertion loss of 8.5 to 10.3dB and a return loss of better than 10dB from 55 to 65GHz. The phase shifter occupies an area of only 0.2mm 2 . To the knowledge of the authors, this is the first 60GHz digitally controlled phase shifter with a phase resolution of 22.5° in silicon reported to date. It is well suited for a 60GHz phased array.

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Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes

Cited by 46 publications

References 20 publications

A 25-Gbps 8-ps/mm transmission line based interconnect for on-chip communications in multi-core chips

A 25-Gbps 8-ps/mm transmission line based interconnect for on-chip communications in multi-core chips

Integrated Silicon Microwave and Millimeterwave Passive Components and Functions

A 60GHz digitally controlled phase shifter in CMOS

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