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Abstract-Viterbi algorithm is widely used in communication systems to efficiently decode the convolutional codes. This algorithm is used in many applications including cellular and satellite communication systems. Moreover, Serializer-deserializers (SERDESs) having critical latency constraint also use viterbi algorithm for hardware implementation. We present the integration of a mixed hardware/software viterbi accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. Later we investigate the performance of viterbi accelerated embedded processor datapath in terms of execution time and energy efficiency. Our evaluation shows that the viterbi accelerated Microblaze soft-core embedded processor datapath is three times more cycle and energy efficient than a datapath lacking a viterbi accelerator unit. This acceleration is achieved at the cost of some area overhead.

Abstract-We present the integration of a multimode Cyclic Redundancy Checking (CRC) accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. We investigate the performance of CRC accelerated embedded processor datapath in terms of execution time and energy efficiency. Our evaluation shows that the CRC accelerated Microblaze SoftCore embedded processor datapath is 153 times more cycle and energy efficient than a datapath lacking a CRC accelerator unit. This acceleration is achieved at the cost of some area overhead.

Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-areanetwork communication and good for future electronic circuits and high-speed systems design.