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The methodology used in the classical methods of design of single pin fittings is reviewed. An alternative for the design of these structural elements using a finite element method is presented. The proposed methodology removes the constraints on the geometry and materials imposed in the classical methods of analysis. The complications of the application of the loading in the finite element method to the fitting sizing problem are discussed in detail and a conclusive procedure of design is presented. Several numerical examples are given and the results obtained are discussed and compared with the classical methods of design.

ID Number: 476) Current Fan Out Wafer Level Packaging (FOWLP) technology, eWLB, has limited heat dissipation capability, as the materials used in, namely the epoxy mold compound (EMC), originally aimed process ability and mechanical stability, but not heat conduction. As eWLB technology expands to WLSiP (Wafer Level System-in-Package) for very high system integration density, combining multiple chips and different components in the same package, the thermal performance becomes a critical factor. In a broader scope, the improvement of its heat dissipation capabilities opens eWLB technology platform also to power applications.A specific difficulty for all encapsulated packages is that the EMC must be electrical insulator, which places challenges both on heat conduction and on reliable mechanical bonding to a usually metallic heat spreader or integrated heat sink. Good heat conductors are, generally, electrical conductors and cannot be used as encapsulate materials. The EMC's are typically organic resins highly loaded with inorganic fillers, but high performance thermal interface material (TIM) are design for metal-metal interfaces, not for organic-metal as required.The paper describes the developments and results achieved towards a Power-eWLB demonstrator, using NANIUM's eWLB technology know-how and manufacturing capabilities. This demonstrator aims the improvement of thermal dissipation capabilities of a typical-size eWLB package, by using novel materials, adhesives and assembly processes suitable for high-volume production. It starts from baseline thermal characterization of eWLB package and the selected measurements methods; discusses the selected materials and techniques for the coupling of the WLSiP body to a heat spreader; and defines the 8mm x 8mm WLSiP capable of multi-pattern heating and dissipating up to 14W.The work done is part of the collaborative European FP7-ICT project NANOTHERM (Innovative Nano-and Micro Technologies for Advanced Thermo and Mechanical Interfaces), together with a consortium of leading IDM, OEM, OSAT, material suppliers and academic/ institutes. 978-1-4799-8609-5/15/$31.00 ©2015 IEEE

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Due to its versatility for high density, heterogeneous integration, Wafer Level Fan Out (WLFO) packaging has recently seen a tremendous growth in a broad array of applications, from telecommunications and automotive, to optical and environmental sensing, while addressing the challenges of the next big wave of the Internet of Things (IoT). In this context, WLFO is continuously being challenged to include new families of MEMS/NEMS/MOEMS sensors, low thermal budget devices and biochips with microfluidics for biomedical applications. Recent developments in WLFO technology by NANIUM [1] demonstrated the implementation of a keep-out-zone (KOZ) mechanism intended to 1st) protect sensitive sensor areas during the backend processing of WLFO wafers and 2nd) create open zones on the Re-Distribution Layers (RDL). This way, the KOZ mechanism provides a physical, direct path from the embedded device to the environment. This is a necessary feature for environment sensing (e.g., pressure) or to create optical paths free of dielectric and protected from the harsh chemistry steps of the WLFO process. This paper describes new developments on KOZ, implemented with SU-8 photoresist as a WLFO dielectric, whose application is a novelty in the WLFO platform. The use of SU-8 and the KOZ with it, addresses some gaps of the current WLFO technology towards the integration of chips with bio-sensitive areas and sensors with low thermal budget. Due to its well-known bio-compatibility and inert behavior, SU-8 can be used as a neutral dielectric to be in direct contact to target fluids (e.g., sera, blood). Also, due to its low curing temperature, SU-8 allows a very low temperature WLFO process and thus the embedding of temperature-limited devices that have been outside the WLFO realm, for example, magneto-resistive or magnetic-spin sensor chips, which degrades its performance above 160°C. More interestingly, SU-8 exhibits a particular non-conformal behavior, which creates very smooth surfaces even over the mildly rough mold compound area of a fan-out package. Adding to this, SU-8 is readily available in the market in a wide range of thicknesses, spanning from 0.5 μm to >100 μm, and further allowing multiple spin coatings to build thick layers. Thus, SU-8 can provide smooth and deep enough channels for microfluidic flow over the chip sensing areas and, at the same time, provide the necessary layer thickness discrimination for the KOZ mechanism. Combining these features, the SU-8 layers in WLFO can play the triple role of 1) RDL dielectric insulation, 2) KOZ mechanism and 3) embedded microfluidic channels as part of the RDL. In summary, besides the unprecedented use of SU-8 in WLFO packaging, KOZ implementation on SU-8 provides a true, attainable bridge between WLFO and integrated microfluidic applications, for biosensing and biomedical applications in general. Outlooking the potentialities of such a merge, a Fan-Out package can embed several chips interconnected by RDL lines, as it currently allows, and also connected by microfluidic channel for multi-point, multi-function biosensing, constituting a true Lab-on-Package, cost-effective solution. Instead of building all sensing areas and microfluidic channels over a large silicon (Si) chip, this solution builds the feed-in, feed-out areas of the microfluidic channel over the inexpensive fan-out area, minimizing the sensing chip area, with the consequent front-end cost reduction.