The resistance switching behaviour of several materials has recently attracted considerable attention for its application in non-volatile memory (NVM) devices, popularly described as resistive random access memories (RRAMs). RRAM is a type of NVM that uses a material(s) that changes the resistance when a voltage is applied. Resistive switching phenomena have been observed in many oxides: (i) binary transition metal oxides (TMOs), e.g. TiO(2), Cr(2)O(3), FeO(x) and NiO; (ii) perovskite-type complex TMOs that are variously functional, paraelectric, ferroelectric, multiferroic and magnetic, e.g. (Ba,Sr)TiO(3), Pb(Zr(x) Ti(1-x))O(3), BiFeO(3) and Pr(x)Ca(1-x)MnO(3); (iii) large band gap high-k dielectrics, e.g. Al(2)O(3) and Gd(2)O(3); (iv) graphene oxides. In the non-oxide category, higher chalcogenides are front runners, e.g. In(2)Se(3) and In(2)Te(3). Hence, the number of materials showing this technologically interesting behaviour for information storage is enormous. Resistive switching in these materials can form the basis for the next generation of NVM, i.e. RRAM, when current semiconductor memory technology reaches its limit in terms of density. RRAMs may be the high-density and low-cost NVMs of the future. A review on this topic is of importance to focus concentration on the most promising materials to accelerate application into the semiconductor industry. This review is a small effort to realize the ambitious goal of RRAMs. Its basic focus is on resistive switching in various materials with particular emphasis on binary TMOs. It also addresses the current understanding of resistive switching behaviour. Moreover, a brief comparison between RRAMs and memristors is included. The review ends with the current status of RRAMs in terms of stability, scalability and switching speed, which are three important aspects of integration onto semiconductors.

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In this research paper, blockchain-based trust management model is proposed to enhance trust relationship among beacon nodes and to eradicate malicious nodes in Wireless Sensor Networks (WSNs). This composite trust evaluation involves behavioral-based trust as well as data-based trust. Various metrics such as closeness, honesty, intimacy and frequency of interaction are taken into account to compute behavioral-based trust of beacon nodes. Further, the composite (behavior and data) trust value of each beacon nodes is broadcast to Base Stations (BS) to generate a blockchain of trust values. Subsequently, the management model discards the beacon node with least trust value and that ensures reliability and consistency of localization in WSNs. The simulated results of the proposed algorithm are compared with the existing ones in terms of detection accuracy, False Positive Rate (FPR) and False Negative Rate (FNR) and Average Energy Consumption (AEC).

In recent years, experimental demonstration of ferroelectric tunnel junctions (FTJ) based on perovskite tunnel barriers has been reported. However, integrating these perovskite materials into conventional silicon memory technology remains challenging due to their lack of compatibility with the complementary metal oxide semiconductor process (CMOS). This communication reports the fabrication of an FTJ based on a CMOS-compatible tunnel barrier HfZrO (6 unit cells thick) on an equally CMOS-compatible TiN electrode. Analysis of the FTJ by grazing angle incidence X-ray diffraction confirmed the formation of the noncentrosymmetric orthorhombic phase (Pbc2, ferroelectric phase). The FTJ characterization is followed by the reconstruction of the electrostatic potential profile in the as-grown TiN/HfZrO/Pt heterostructure. A direct tunneling current model across a trapezoidal barrier was used to correlate the electronic and electrical properties of our FTJ devices. The good agreement between the experimental and theoretical model attests to the tunneling electroresistance effect (TER) in our FTJ device. A TER ratio of ∼15 was calculated for the present FTJ device at low read voltage (+0.2 V). This study suggests that HfZrO is a promising candidate for integration into conventional Si memory technology.

The present work reports the fabrication of a ferroelectric tunnel junction based on a CMOS compatible 2.8 nm-thick Hf0.5Zr0.5O2 tunnel barrier. It presents a comprehensive study of the electronic properties of the Pt/Hf0.5Zr0.5O2/Pt system by X-ray photoelectron and UV-Visible spectroscopies. Furthermore, two different scanning probe techniques (Piezoresponse Force Microscopy and conductive-AFM) were used to demonstrate the ferroelectric behavior of the ultrathin Hf0.5Zr0.5O2 layer as well as the typical current-voltage characteristic of a ferroelectric tunnel junction device. Finally, a direct tunneling model across symmetric barriers was used to correlate electronic and electric transport properties of the ferroelectric tunnel junction system, demonstrating a large tunnel electroresistance effect with a tunneling electroresistance effect ratio of 20.