N-path filters exploiting switched-series-R-C networks can realize high-Q blocking-tolerant band-pass filters. Moreover, their center frequency is flexibly programmable by a digital clock. Unfortunately, the time variant nature of these circuits also results in unwanted signal folding. This paper proves analytically that folding can be reduced and band pass filtering can be improved by adding an inductance in series with the switched-R-C network. In contrast, a shunt capacitor degrades band-pass filter performance. The interaction between the reactive series impedance and the switched capacitors of an N-path filter complicates analysis due to memory effects associated with reactive components. Assuming identical signal paths with 1/ duty cycle, we show it is possible to solve the set of differential equations, by assuming that the signals in each path only differ in delay. Analytical equations are verified versus simulations, and the benefits in filter properties and reduction in signal folding are demonstrated.Index Terms-Cognitive radio, commutated network filters, filter, frequency translated filtering, linear periodically time variant circuit, N-path filter, reconfigurable filter, software defined radio, switched capacitor filters, tunable filter. 1549-8328

Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible with opamp-RC techniques. The inverter's class-AB behavior, together with the high transconductance per quiescent current, results in a high dynamic range per power when optimally biased [3]. The major disadvantage of traditional inverter-based Gm-C filters is that they are tuned with the supply voltage (VDD), hence requiring a finely controllable supply. Voltage regulators used to accomplish this imply a voltage headroom (including margin for tuning) and degrade total power efficiency by tens of percent. In this paper, we show that by exploiting body biasing in an Ultra-Thin BOX and Body, Fully-Depleted SOI (UTBB FD-SOI) CMOS technology, we overcome the requirement for a tunable VDD in inverter-based Gm-C filters, while achieving a high linearity over a wide supply voltage range. Without body biasing, Gm changes and linearity is degraded. For high VDD, the inverter behavior is compressive (mobility reduction), while for low VDD it is expansive (exponential region). Only one VDD results in a flat Gm-curve, which means that it produces little 3rd order distortion. Body biasing can be applied to tune Gm back to its nominal value over different VDD, without linearity degradation, as illustrated in the bottom right plot of Fig. 5.5.1. We apply this technique to a low-pass (LP) Gm-C filter to keep the cut-off frequency (Fc) constant and to guarantee high linearity over a 300mV supply voltage range. Local supply decoupling is still required, but the separate voltage regulator can be omitted. Without this technique, the same supply variation would have shifted the cut-off frequency between 110 and 650MHz and degraded IIP3 by more than 10dB.The LP filter topology shown in Fig. 5.5.2 is derived from a 3rd order, doubly terminated Butterworth LC ladder prototype using gyrator synthesis [1]. The transconductors and MOM capacitors are sized for a nominal Fc of 450MHz. The use of 110nm gate

This paper describes a combination of a Weaver mixer and an N-path filter for a superheterodyne receiver with a reconfigurable frequency plan. It uses an N-path topology driven with two different frequencies, effectively realizing a frequency shift together with band-pass filtering. To reduce transfers via harmonics other than the fundamental, a harmonic rejection scheme is used. A 28 nm FDSOI CMOS implementation with 30 dB harmonic rejection and an out-of-band IIP3 of >20 dBm is demonstrated.

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N-path filters can offer high-linearity high-Q channel selection filtering at a flexibly programmable RF center frequency, which is highly wanted for Software Defined Radio. Relying on capacitors and MOSFET switches, driven by digital non-overlapping clocks, N-path filters fit well to CMOS and benefit from Moore's law. The basis of this filtering is the linear periodically time variant (LPTV) behaviour of a switch-R-C series circuit, which realizes frequency translated filtering, where a baseband filter characteristic is shifted around the switching frequency. This paper reviews the basic concept of N-path filters and recent developments, with special attention to possibilities to reduce power consumption by increasing the impedance level. The basic operation of the switch-R-C kernel that is at the core of N-path filtering is reviewed in terms of transfer function and noise performance.