Abstract. Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we analyse some crucial timing behaviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using the model of parametric timed automata and model checker HYTECH, we formally derive a set of linear constraints that ensure the correctness of the response times of the memory. We are also able to infer the constraints characterizing the optimal setup timings of input signals. We have checked, for two different implementations of this architecture, that the values given by our model match remarkably with the values obtained by the designer through electrical simulation.

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As CMOS technology continues to downscale to a deep submicron level (40 nm and beyond), Soft Oxide Breakdown (SBD) is becoming a real problem that could lead to a serious degradation in the performances and the functional operations of SoC. In this paper we study the SBD, using two models, and quantify its impact on the functionality of a 40 nm SRAM memory.Keywords-Soft Oxide Breakdown (SBD); Transistor SBD models, SRAM functional failure; Delay drift. I. SRAM LIBRARY OVERVIEWThe impact of intrinsic reliability can have significant impact on Static Random Access Memories (SRAM) libraries as they are more susceptible to functional failure [1]. Besides, SRAM libraries are performance bottlenecks in high-performance VLSI circuits, and occupy a majority of on-chip silicon area while requiring good tolerance throughout the life of usage.A SRAM library is typically divided in 4 main blocks. The operation in the clock cycle is computed in the control block. When a read or a write cycle is performed, the address is chosen by the decoder block before selecting the right word inside the memory array. In parallel, the input/output block is either collecting the data from the memory array for a read cycle, or collecting from outside of the memory the data which will be saved in the memory array for a write cycle (Fig. 1).In order to reach the highest level of performance, specific design techniques are implemented in SRAM libraries: dynamic logic for control and decoder, sense-amplifiers for reading the data in the bit-cell. However, this strategy yields the generation of enabling signals like internal clock circuitry which mimics the longest timing path. II. SBD IMPACT ON SRAM LIBRARY A. Design sensitivity analysisIn a complex design as an SRAM (more than 10 5 MOS), the defect cannot be simulated on each transistor. As described in fig.1, the main critical parts of the design have been selected to simulate the SBD impact.Firstly, the SBD effect is statistical: the structure which is covering the biggest area must be tested. In the SRAM context, the majority of the area is covered by the memory bit cell (memcell). As a consequence, the bit cell has been selected.Secondly, this SRAM is using a complex regulation loop. If this loop is broken, the functionality of the memory is lost. Several critical parts in this loop have been selected.Finally, the design structures itself has been studied. The senseamplifier has been selected because it uses a fully symmetric structure in order to detect voltage differences between two nets during read cycles. If this functionality is not fulfilled, the data read is corrupted. B. SBD electrical modeling strategyTo represent the SBD, we have used the two electrical models used in the literature to emphasis a potential difference between them (Fig. 2):-The first one is the traditional Ohmic model, which consists of connecting a resistance R SBD between the Gate and the diffusion (Drain or Source) to model a current leakage path (see Fig. 2(i)).-The second one, which can be obtained via transis...

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This paper introduces for the first time a new test structure for electromigration which allows increased statistics and reliability tests in a testchip under typical High TemperatureOperating Life experimental ranges. Following the electrical analysis, a large panel of failure analysis methodologies was suitably used to categorize defects such as size, location, resistance impact, etc. This thorough analysis allows us to confirm that silicon failures are accurately predicted by our electromigration checker, based on reliability design rules.