The increase of test time of embedded DRAM (e-DRAM is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis finction on chip as Built In Self Repair (BISR). BISR is performed at 1661MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7mm2 about 2% of conventional SOC devices. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM functional test time was reduced about 20% less than conventional method at wafer level testing. Moreovel; the results of e-DRAM test and repair analysis using BISR is almost coincident with conventional method.

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In today 's computing environment, novel memory devices with non-volatile