Test cost reduction by at-speed BISR for embedded DRAMs

Abstract

The increase of test time of embedded DRAM (e-DRAM is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis finction on chip as Built In Self Repair (BISR). BISR is performed at 1661MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7mm2 about 2% of conventional SOC devices. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM functional test time was reduced about 20% less than conventional method at wafer level testing. Moreovel; the results of e-DRAM test and repair analysis using BISR is almost coincident with conventional method.

Evaluating the Yield of Repairable SRAMs for ATE

“…Moreover, testing of embedded memories (SRAM and DRAM) incurs in additional costs due to the large test time and ATE performance (such as for "at speed" testing). To lower test costs and to allow tester designers to meet memory requirements, discrete Fourier transform (DFT)/built-in selftest (BIST) and built-in self-repair (BISR) solutions have been proposed [2]- [5]. Yield evaluation can be used in selecting an appropriate testing strategy; when the expected yield is high, BIST or BISR solutions may be preferred; otherwise, more expensive ATE solutions are available.…”

Saturating counters: application and design alternatives

“…The use of BISTDR not only enables permanent memory repair following manufacturing (hard repair), but also every time the system is powered up (soft repair). Hard repair can be done by laser blown fuses or by writing non-volatile re-configuration flip-flops, while soft repair uses only the latter [5,6,7].…”

“…In [1] Jones and Swartzlander have compared the design of parallel counters using only (3,2) or (2,2) counters to designs using more complex counters like (7,3), (15,4) and (31,5). They have analyzed the delay and area of different implementations and concluded that designs based on (3,2) and (2,2) counters only are generally superior.…”

“…Such designs use different basic building blocks like (3,2) counters, (7,3) counters and the like [3]. An ( , ¡ ) parallel counter has input bits and produces a ¡ -bit binary count of its inputs that are 1.…”

Yield evaluation methods of SRAM arrays: a comparative study

“…To lower test costs, and to allow tester designers to meet different memories requirements, DFT/BIST and BISR solutions have been proposed [4] [5] [2] [3]. With the increase in memory size, efficient solutions are required to maintain acceptable production yield [6].…”