INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0740-7475Although parity prediction arithmetic operators are compatible with systems checked by parity codes, they are not secure against single faults. The authors determine the necessary conditions for fault secureness and derive designs embodying these conditions

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Parity prediction arithmetic operators are compatible with data paths and memory systems checked by parity codes. The authors extend their theory for achieving fault-secure design of parity prediction multipliers and dividers to Booth multipliers using operand recoding

ABSTRACT:The basic drawback of parity prediction arithmetic operators is that they may not be fault secuw for single faults. In a recent work we have proposed a theory for achieving fault secure design for parity prediction multipliers and dividers. This paper has not considered the case of Booth multipliers using operand recoding. This case is analyzed here. Parity prediction logic and fault secure implementation for this scheme is derived.

Abstract:satellite using a digital signal processor. The main motivation of this study is the attitude control system of the the aim of testing the adequacy of the adopted control. The next steps had included an analysis of discretization modulator. The validation tests used a scheme of co-simulation, where the model of the satellite was simulated inand required time to achieve a given mission accuracy are determined, and results are provided as illustration.