Moving into the future world, life will be getting more easier and easier because of internet of things (IOT). Nowadays with increased need for surveillance, monitoring and data collection IOT has become more important. Today almost all devices are equipped with sensors and are controlled by controllers such as from cars to vacuum cleaners, rockets to Vernier calipers, air conditioners to water pumps. By embedding intelligence in everyday objects, they turned into smart devices and can be controlled from anywhere in the world. This paper discusses about internet of things and its advantages and disadvantages. It discusses the applications of IOT in various fields such as city, agriculture, remote monitoring, smart street light, etc. This paper also tells about the history of IOT.

The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware heavily uses cycle-accurate simulation of register-transfer-level (RTL) designs. The best software RTL simulators can simulate designs at 1-1000 kHz, i.e., more than three orders of magnitude slower than hardware. Faster simulation can increase productivity by speeding design iterations and permitting more exhaustive exploration.One possibility is to use parallelism as RTL exposes considerable fine-grain concurrency. However, state-of-the-art RTL simulators generally perform best when single-threaded since modern processors cannot effectively exploit fine-grain parallelism.This work presents Manticore: a parallel computer designed to accelerate RTL simulation. Manticore uses a static bulk-synchronous parallel (BSP) execution model to eliminate runtime synchronization barriers among many simple processors. Manticore relies entirely on its compiler to schedule resources and communication. Because RTL code is practically free of long divergent execution paths, static scheduling is feasible. Communication and synchronization no longer incur runtime overhead, enabling efficient fine-grain parallelism. Moreover, static scheduling dramatically simplifies the physical implementation, significantly increasing the potential parallelism on a chip. Our 225-core FPGA prototype running at 475 MHz outperforms a state-of-the-art RTL simulator on an Intel Xeon processor running at ≈ 3.3 GHz by up to 27.9× (geomean 5.3×) in nine Verilog benchmarks.

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