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Three-dimensional (3D) interconnection technology offers several electrical advantages, including reduced signal delay, reduced interconnect power, and design flexibility. 3D integration relies on through-silicon vias (TSVs) and the bonding of multiple active layers to stack several die or wafers containing integrated circuits (ICs) and provide direct electrical interconnection between the stacked strata. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in stacked 3D ICs are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multidie stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of a single-valued junction-to-air thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package and heat sink thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the multidie stack. The improvement required in package and heat sink thermal resistances for a 3D logic-on-memory implementation to be thermally feasible is quantified. An increase in maximum temperature in a 3D IC compared to an equivalent system-in-package (SiP) is predicted. This increase is found to be mainly due to the reduced chip footprint. The increased memory die temperature in case of memory-on-logic integration compared to a SiP implementation is identified to be a significant thermal management challenge in the future. The results presented in this paper may be useful in the development of thermal design guidelines for 3D ICs, which are expected to help maximize the electrical benefits of 3D technology without exacerbating thermal management issues when implemented in early-stage electrical design and layout tools.Index Terms-Die stacking, electrical-thermal co-design, junction-to-air thermal resistance, three-dimensional (3D) integrated circuits (ICs), through-silicon via (TSV).

Six unsaturated fluorocarbon (UFC) gases as well as a fluorinated ether were examined for dielectric etch and global warming emissions performance and compared to three perfluorocompound (PFC) gases. All of the gases were capable of etch performance comparable to that of a typical C3F8 process, while exhibiting superior global warming emissions performance compared to the PFCs. A low-flow hexafluoro-2-butyne process was found to have a significant emissions benefit, showing a normalized emissions reduction of 88.2% compared to the C3F8 process. Two other C4F6 isomers (hexafluoro-1,3-butadiene and hexafluorocyclobutene) also exhibited reductions greater than 80%, while hexafluoropropene and octafluorocyclopentene exhibited emissions reductions greater than 70% compared to the typical C3F8 process. For the C4F6 isomers, a large portion of the emissions were a result of CHF3 formation with photoresist as the sole source of the hydrogen. An extended 4 min etch with hexafluoro-1,3-butadiene resulted in a deep via with an aspect ratio of 5:1, very high selectivity to photoresist, and no evidence of etch stopping. © 2002 The Electrochemical Society. All rights reserved.

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