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Electromigration failure in flip-chip bumps has emerged as a major reliability concern due to potential elimination of Pb from flip-chip bumps and a continuous drive to increased IO density resulting in a reduction of bump size and pitch. Traditionally, flip-chip interconnects incorporate a high Pb bump soldered with a SnPb eutectic paste to the substrate or another die. However, because of RoHS directives, the industry is responding with Pb free bump development, such as SnAg bump with SAC solder or Cu Pillar with SAC/SnAg solder. Although a number of recent publications deal with electromigration reliability of Pb free and Cu Pillar bumps, a gap exists in terms of their performance comparison with high Pb and SnPb solder on the same bump geometry. The available test data is based on different test vehicles and it becomes difficult to determine the relative performance of these different metallurgies under accelerated test conditions. In addition, not all published data provides the essential parameters of Black's equation to determine the performance and reliability for actual use conditions. This paper attempts to fill this gap by comparing electromigration performance of High Pb, SnPb eutectic, SnAg, and Cu Pillar bumps using the same test vehicle. A special test vehicle was designed with daisy chain structures for electromigration testing and the packages we assembled on test cards. The testing is being done using five (5) stress conditions (combination of current and temperature) to estimate the current density exponent, n, and activation energy, Ea, parameters for Black's equation. The reliability data as well as failure modes for these bump metallurgies will be presented in the paper.

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