An ultra-short pulse current–voltage (I–V) measurement technique has been applied to high-κ gate transistors to investigate the effects of fast transient charging. It is shown that the fast electron trapping may contribute to the degradation of transistor performance (i.e., low mobility) observed with direct current (DC) characterization methods, as well as pulse techniques in the tens of microseconds range and above. In particular, in the samples with significant electron trapping, the drain current in the saturation regime is shown to improve by up to 40% from its DC values when the characterization is performed with pulse I–V measurements in the nanosecond range.

Changes in the composition of atomic layer deposited, uncapped hafnium dioxide films, as a function of anneal temperature, have been evaluated by several advanced analytical techniques including; x-ray reflectivity, high-resolution transmission electron microscopy, and medium energy ion scattering. It is shown that such measurements of the high-k/Si interface layer are inconclusive and may be misinterpreted to suggest the presence of an HfxSi1−xO2 (x∼0.5) transition layer. It is also demonstrated that high-temperature anneal of uncapped films may result in the formation of voids which propagate through the dielectric layer into the silicon substrate. Trends associated with defect generation, interfacial oxide growth, and the low probability of material intermixing during anneal processing are discussed.

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Electron traps in ALD and MOCVD HfO2 and HfSiO high-k dielectrics were investigated using both conventional DC and pulse measurements. It was found that the traps in the gate stack could be associated with defects of different activation energies and capture cross-sections. This points to potentially different origins of the electrically active defects, which can be either intrinsic or process-related. Structural non-uniformity of the high-k film, associated with grain formation and phase separation, may lead to variation of electrical properties of the gate dielectric along the transistor channel. Effects of such dielectric non-uniformity, as well as electron trapping, on the measured transistor mobility were evaluated.