The conception and assembly of an experimental Hybrid Electric Vehicle based on the combination of human energy contribution and photovoltaic solar energy is presented in this manuscript. The vehicle has a battery for storing the energy provided by both systems. The application's aim is to achieve the lowest possible energy consumption for the vehicle's movement, with photovoltaic modules as the main electricity source. The development of the solar vehicle was motivated by a Latin-American solar vehicles race about 1000km across the Atacama Desert in Chile, South America. The main constructive aspects, energy issues and experimental results are presented.

Autonomous Underwater Vehicles (AUVs) are suitable platforms for a wide type of applications in the oceanic environment. These applications are developed in various fields such as scientific surveying, off-shore industry and defense. The employment of AUVs requires less human support and reduces operation costs. Due to the changing marine environment these vehicles must deal with uncertain and hostile conditions to perform its tasks. In the marine robotics matter, the INTELYMEC group has developed in 2012 an AUV prototype called Ictiobot, a low cost experimental platform for multipurpose missions. In this paper an upgrade of the original prototype is presented, the Ictiobot-40, conceived to perform acoustic imaging surveying missions of up to two hours and maximum depths of 40 meters. The new software and hardware architectures and mechanical structure improvements, are detailed. In addition to these technical details, initial experimental results of the AUV performance in quiet waters will be discussed. Also, the new approaches for systems under development are presented.

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This work is part of a project that studies the implementation of neural network algorithms in reconfigurable hardware as a way to obtain a high performance neural processor. The results for Adaptive Logic Network (ALN) type binary networks with and without learning in hardware are presented.The designs were made on a hardware platform consisting of a PC compatible as the host computer and an ALTERA RIPP10 reconfigurable board with nine FLEX8K FPGAs and 512KB RAM. The different designs were run on the same hardware platform, taking advantage of its configurability.A software tool was developed to automatically convert the ALN network description resulting from the training process with the ATREE 2.7 for Windows software package into a hardware description file. This approach enables the easy generation of the hardware necessary to evaluate the very large combinatorial functions that results in an ALN.In an on-board learning version, an ALN basic node was designed optimizing it in the amount of cells per node used. Several nodes connected in a binary tree structure for each output bit, together with a control block, form the ALN network. The total amount of logic available on-board in the used platform limits the maximum size of the networks from a small to medium range.The performance was studied in pattern recognition applications. The results are compared with the software simulation of ALN networks.