In this paper we present synchronisation techniques for hard real-time (HRT) capable execution of parallelised applications on embedded multi-core processors. We show how commonly used software synchronisation techniques can be implemented in a time analysable way based on the proposed hardware primitives. We choose to implement the hardware synchronisation primitives in the memory controller for two reasons. Firstly, we remove pessimism in the WCET analysis of parallelised HRT applications. Secondly, we enable that the implementation of synchronisation techniques is mostly independent of the chosen instruction set architecture (ISA) which allows to use the existing ISAs without enhancements. We analyse the presented synchronisation techniques with the static worstcase execution time (WCET) analysis tool OTAWA. In summary, our specifically engineered synchronisation techniques yield a tremendous gain on the WCET of parallelised HRT applications. I. INTRODUCTIONFor a long time research in parallel applications and architectures was bound to the domain of high-performance computing. With the upcoming of multi-core processors, parallelisation became also important in other domains, namely desktop end-user systems and embedded systems as well. However, embedded systems have different needs and must fulfil other requirements than high-performance systems. Today's HRT applications in the automotive, avionic or machinery industry are executed on single-core processors. The new trend of using multi-cores in safety-critical domains sparks off research on running HRT tasks in parallel with other tasks to execute mixed-critical application workloads. Our research goes even one step further: we target multi-core execution of parallelised HRT tasks without sacrificing timing guarantees.In this paper, we focus on the timing predictability of synchronisation in parallelised HRT applications using the static WCET analysis tool OTAWA [1]. The contributions of this paper are as follows: we show that specifically engineered software synchronisation techniques, busy-waiting as well as blocking synchronisation methods, are timing analysable. We assess these synchronisation primitives and their hardware respectively software implementation with respect to their impact on the WCET, and the possible gain for the WCET of parallelised HRT applications.The presented synchronisation techniques can be implemented independently of the ISA, as the logic for the hardware synchronisation primitives is nested in the memory controller.

M3S is an academic shared-memory multiprocessor.The memory is divided into modules. Each processor (through its cache) has an access to each memory module only through a high-throughput private serial link, Each memory module has several serial ports lhat are connected, in parallel, to the memory. The data coherency is maintained by a hardware direclory-based scheme.The interconnection network has no bottleneck since each processor has its private path to each memory module. The high bit rate of the serial links is the most important technical problem for the design of this proiorype. Synchronous solurions have been chosen inthe prototype because of their greater simplicity. The data rate on the serial links is 800 Mbitls. We explain. in this paper, different choices we have mude to realize rhis project with one memory module and sixteen processor modules.