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No abstract

Debs pela orientação de extrema competência, confiança no meu trabalho e amizade. Aos professores do Departamento de Engenharia de Estruturas da ESSC pelos conhecimentos transmitidos e amizade. Aos funcionários do Departamento de Engenharia de Estruturas pelo apoio e aconchego. Ao amigo e colega Eduardo Walter pelas contribuições profissionais e companheirismo destes dois anos de mestrado e da própria graduação. À amiga Conceição de Maria (Mana) pela correção do texto e principalmente pelo apoio emocional e incentivo profissional sem os quais teria sido bem mais difícil completar esta tarefa. Ao meu pai pelo apoio de todas as formas, e a minha mãe, em memória, que também com certeza de onde estiver estar ao meu lado. Aos familiares que sempre me incentivaram ao aprendizado. Aos amigos e colegas do Departamento pelo carinho e sabedoria que sempre transmitiram.

As high-performance, compact semiconductor devices approach physical limitations on the number of input and output pins, board designers increasingly rely on microvias to fan out signals in facilitating board layout. These highly compact and high-density designs are driving microvias with even more closely-packed, smaller-diameter holes and thinner traces. One such embedded computer system used in aerospace applications has 17,018 microvias. Acceptance Testing (AT) criteria includes environmental stresses to ensure flight worthy status of hardware. Honeywell AT was able to help identify three failures that after extensive investigation along with Scanning Electron Microscopy (SEM) analysis were found to be attributed to microvia failures. The three failed Printed Wiring Assemblies (PWA) were two Processor boards, and one Input/Output (I/O) board. For the Processor boards, we have confirmed microvia separation without identifying root cause. For the I/O board, the cause of the microvia separation was identified as delamination within the Thermount® surface layer. After a thorough failure investigation for each of the failures, a joint failure review board including members from Honeywell, customers, and the Printed Wiring Board (PWB) vendor was held. The conclusion of the meeting was that root cause had not been identified, and experiments were designed to determine either root cause or exonerate Honeywell's manufacturing process. The complete process beginning with board construction at the PWB vendor to board integration into the embedded computer system was evaluated for potential root cause. Honeywell engineers developed Six Sigma Design of Experiments (DOE) to validate Honeywell's Surface Mount Technology (SMT) processes, specifically the combination of vapor phase reflow and exposure to humidity. Two different experiments were developed: one for Interconnect Stress Test (IST) coupons representative of printed wiring boards and another using flight PWBs. Highresolution resistance measurements in milliohm range were taken before and after they were subjected to humidity and thermal conditioning. Resistance changes were analyzed for indications of potential suspect circuits with microvias. Results verify that the tested levels of humidity, vapor phase profiles, and moisture re-absorption do not have an impact on microvia integrity. 1 2